EDT VisionLink F Series User Manual Download Page 26

EDT, Inc. 

2019 April 29 

26 

VisionLink F-series 

Troubleshooting 

 

 

 

Linux 

Try any of the following... 

 

 

Failure during installation may be due to system package dependencies. Make sure the following packages are 
installed on your system... 

 

make 
gcc 
libtiff 
linux kernel headers 

For example 

 on Ubuntu, to install the  

libtiff 

library, enter... 

sudo apt-get install libtiff4-dev 

After all needed packages are in place, run 

make 

from the installation directory (see 

Installation on page 8

) t

complete installation. 

 

 

Uninstall and then reinstall your existing EDT installation package. To uninstall, use the programs in the installation 
directory (see 

Installation on page 8

),... 

 

  If the package was installed using  

package

.run

, remove it with 

./uninstall.sh. 

  If the package was installed using 

rpm --install package, 

remove it with 

rpm --erase 

package

 

Download and install the latest EDT installation package (see 

Installation on page 8

). 

 

NOTE 

New Linux versions often require an updated device driver, so if you are using a new or updated Linux kernel and 
you have trouble with the EDT installation or device access, check to see if a new EDT installation package is 
available. 

 

Corrupted Images, Slow Acquisition, Timeouts, Data Loss 

Corrupted images, slow acquisition rates, repeated timeouts, or data loss usually indicate that the bus is too slow or the 
driver is misconfigured. To correct this issue... 

 

 

Verify that the camera configuration file is the correct one for your camera and operating mode; see 

Setting the 

Camera Model on page 9

. 

 

Verify that the EDT board is in a PCIe slot that is wired electrically (not just physically) to support the number of 
lanes provided by the board. For example, a four-lane board requires a slot that has four or more lanes. Also, note 
that some motherboards will 

“split”

 lanes between two slots, so that two x8 slots will become x4 if both are occupied. 

 

 

Determine the bandwidth required by your camera, and then ensure that both the board and the host can sustain 
the required throughput. For fastest full-mode cameras, your frame grabber and your host bus both must support 
eight lanes. For multiple camera installations, the combined data rates should not exceed that of the board(s) in- 
stalled. 

 

 

Verify that the firmware file you loaded is the correct one for your camera and your mode of operation (base, me- 
dium, or full mode); see 

Firmware: FPGA Configuration (.bit) Files on page 22

. 

 

Eliminate other devices, if any, that may be reducing the available bus bandwidth. 

 

 

Consult 

Requirements on page 8 

to verify that your setup meets bus and throughput requirements. 

 

 

When updating to a new device driver, always recompile and relink applications that use EDT libraries (see 

Firm- 

ware: FPGA Configuration (.bit) Files on page 22

). 

 

For more information, see 

Problems With Bandwidth

. 

Summary of Contents for VisionLink F Series

Page 1: ...User s Guide VisionLink F Series Camera Link Frame Grabbers for PCI Express Date 2019 April 29 Rev 0012...

Page 2: ...erence received including interference that may cause undesired operation This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of FCC Rul...

Page 3: ...ors officers employees or agents be liable to Buyer for any consequential incidental or indirect damages including damages for business interruptions loss of business profits or information and the li...

Page 4: ...ernal Triggering Pins 19 Simulation and Testing 20 Programming 21 Building or Rebuilding an Application 21 Compiling vlviewer 22 Firmware FPGA Configuration bit Files 22 Checking and Loading the Firmw...

Page 5: ...EDT Inc 5 Footer Format 33 IRIG API 35 Revision Log 37...

Page 6: ...IRIG B 019 14836 Full height backpanel 1 SDR 019 14852 Full height backpanel 2 SDRs 128 MB DDR3 IRIG B Lemo VisionLink F4 PCIe x4 Base TBD Half height backpanel full 019 14856 Full height backpanel 01...

Page 7: ...ar EDT product go to edt com and open the relevant product page There you ll see links to that product s datasheet specifications user s guide and other resources In addition the resources below may b...

Page 8: ...o save it elsewhere the package is saved in the default installation directory specified below The Windows default installation directory is C EDT pdv The Linux default installation directory is opt E...

Page 9: ...ur camera model and operating mode For specifying a non default unit and channel and other options see initcam Example and Utility Applications on page 13 and the Camera Configuration Guide Related Re...

Page 10: ...1 This example is useful if for instance you are using one board with two base mode cameras and you want the GUI to access the camera on channel 1 NOTE In Windows the command line is a property of the...

Page 11: ...tion Units boards connectors and channels are always enumerated from 0 Figure 2 also shows the status indicator LEDs see LEDs on page 12 which are enumerated in the same way Figure 2 Illustration of e...

Page 12: ...ly serial_baud serial_init serial_binit and other serial_ directives can be used to send serial commands when the system is initialized These are described in the EDT Camera Configuration Guide see Re...

Page 13: ...tiondirectory Example and Utility Applications EDT provides a variety of example utility and diagnostic applications All can be run from the command line using Unix style options and arguments To help...

Page 14: ...e camera settings such as integration time tune image acquisition in certain ways and detect errors Several of the most useful options are u unit The unit number if multiple boards are installed defau...

Page 15: ...re03 bmp enter simple_take N 4 l 4 b picture simplest_take The simplest example application showing only how to open the device acquire an image check for timeouts and close the device For simplicity...

Page 16: ...ewer pdvshow etc 4 Run dvinfo If multiple boards are installed you may find it helpful to add the optional flag u unit replacing unit with the unit number The default is 0 for the first board for deta...

Page 17: ...the exposure time for example use set for the Dalsa 1M60 API subroutine pdv_set_exposure Camera specific range and units Triggered by EDT Board Fixed Period In this mode the board sends a fixed period...

Page 18: ...C1 API subroutine pdv_set_exposure Microsecond units range 0 25500 External Trigger Direct to Camera In this mode a trigger is sent from an external source directly to the camera bypassing the board T...

Page 19: ...0 and then is passed from the board to the camera via a camera control line typically CC1 to trigger line output Additionally a secondary TTL signal is sent from an external device to the board via tr...

Page 20: ...ing In addition to the physical channels 0 and 1 each VisionLink frame grabber has a phantom channel 2 that reads self generated sample data useful for testing the board hardware and software with no...

Page 21: ...n programming interface API for all supported operating systems so an application written for one EDT product is designed to work with other EDT products with minimal modification any exceptions such...

Page 22: ...ur system and in your path at a minimum the Qt Core and Development libraries are required See http qt project org for Qt information and downloads The method for installing Qt4 varies depending on th...

Page 23: ...the firmware on the board is the same as the firmware in the installation package If they differ you ll see an error message but this does not necessarily indicate problems if your application is wor...

Page 24: ...or to the appropriate flash fpga subdirectory 2 Power off the host and board 3 To avoid later confusion remove any other EDT boards from the host 4 On the EDT board with the corrupted firmware move th...

Page 25: ...ally a VisionLink board will not work in a slot dedicated to graphics display cards or a slot wired for fewer lanes than the number specified for instance a four lane board will not work properly in a...

Page 26: ...dicate that the bus is too slow or the driver is misconfigured To correct this issue Verify that the camera configuration file is the correct one for your camera and operating mode see Setting the Cam...

Page 27: ...irements Consider the number of cameras and the speed of the cameras you are using The bus bandwidth may be adequate for some configurations but inadequate for configurations with more or faster camer...

Page 28: ...he underlying EDT DMA library The EDT message handler library provides generalized error and message handling for EDT software libraries and can be helpful in debugging your programs See the EDT messa...

Page 29: ...inner shield ground inner shield ground 2 25 X0 Y0 Y0 15 12 X0 Y0 Y0 3 24 X1 Y1 Y1 16 11 X1 Y1 Y1 4 23 X2 Y2 Y2 17 10 X2 Y2 Y2 5 22 Xclk Yclk Yclk 18 9 Xclk Yclk Yclk 6 21 X3 Y3 Y3 19 8 X3 Y3 Y3 7 20...

Page 30: ...k F1 FPGA boot select Normal Protected optional Lemo with adapter Quad LED 10 8 6 4 2 9 7 6 3 1 Test points optional secondary SDR26 1 Triggering pins DVAL LVAL FVAL PCLK primary SDR26 0 pin hole Not...

Page 31: ...ed Reserved 10 Ground Ground LEMO CONNECTOR OPTIONAL Pin VisionLink F1 VisionLink F4 1 Trigger 1 Trigger 1 2 3 3V 3 3V 3 Trigger 0 Trigger 0 4 Trigger 0 Trigger 0 5 IRIG B IRIG B 6 Trigger 1 Trigger 1...

Page 32: ...backpanel equipped with ribbon cabling and one or two 9 pin D connectors The diagram below illustrates the single D connector setup Connectors Transceivers Secondary Primary Any EDT framegrabber Trigg...

Page 33: ...IRIG1 is now obsolete In addition to the IRIG time value the footer contains a frame counter as well as space for a 64 bit timestamp computed as Unix seconds and fractionalseconds For information on c...

Page 34: ...For IRIG time the raw format is 6 bits seconds 6 bits minutes 5 bits hours 9 bits days 6 bits years Unix seconds seconds since 1 1 1970 without leap seconds 40 MHz count 12 4 u_int Counts using onboa...

Page 35: ...ok 1 u_char pps_ok 1 u_char had_irig_error 1 u_char had_pps_error 1 status u_char reserved 3 double timestamp holds a 64 bit unix seconds time This must be filled in by software Irig2Record IRIG API I...

Page 36: ...e DMA stream from the board this pointer will be overwritten when this buffer is used again enter irig2Record pdv_irig_get_footer PdvDev pdv_p u_char imagedata To compute the Unix time from the counts...

Page 37: ...y A comprehensive user guide for vlviewer is available via the application s Help menu and replaced To specify options run with To invoke with other than the default 0 0 unit and channel run 20160129...

Page 38: ...eries Frame Grabbers to F1 diagram added optional Lemo p 32 Additional External Inputs Via Berg or Optional Lemo updated pinouts 20140630 PH CH 0003 8 In Table 1 for VisionLink F4 Gen2 updated 850MB s...

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