EV8AQ160-DK
60
BDC- 1-Sep-10
e2v semiconductors SAS 2010
5.3. VHDL CODE
VHDL Top level simplify block diagram
VHDL simplify SERDES diagram for each ADC output bit
SERDES
SERDES
SERDES
SERDES
A [AL AH]
ADR
B [BL BH]
BDR
C [CL CH]
CDR
D [DL DH]
DDR
FIFO
RAM
FIFO
RAM
FIFO
RAM
FIFO
RAM
SPI
Reg File
DDR clock
Output Data
I/O Buff
I/O Buff
S
E
R
D
E
S
X
8
BUFR/4
FIFO
