E.F. Johnson Company Summit DM 975x, Service Manual

Page: 111 / 216

CIRCUIT DESCRIPTION
6-6
August 1993
Part No. 001-9750-001
programming circuitry. The basic operation was
described in Section 6.2.1.
Channel Programming
Channels are selected by programming the R, N,
and A counters in U801 to divide by a certain number.
The programming of these counters is performed by
the microprocessor using data stored in EEPROM
U406. These counters are programmed as follows:
Data to be loaded into U801 is first clocked
through shift register U802. It is fed into U801 on the
DATA input (pin 10) and clocked in a bit at a time by a
low-to-high transition on the CLOCK input (pin 9).
Data is first loaded into the 1-bit register (see
Figure 6-2) and then into the 7-, 10-, and 14-bit regis-
ters. The last bit is present in the 1-bit register, and it
determines which counter will be programmed. If this
bit is a 1, the data is latched by all three counters when
the latch ENABLE input (pin 11) goes high. If it is a 0,
it is latched by only the A and N counters.
U801 Operation
As stated earlier, the divide numbers of the
counters in U801 are chosen so that when the VCO is
operating on the correct frequency, the fR and fV
phase detector inputs are the same frequency.
The fR input is produced by dividing the 17.500
MHz TCXO frequency on pin 1 by 1400. This
produces an fR frequency of 12.5 kHz. Using this
frequency allows channels to be changed in 12.5 kHz
steps. A 12.5 kHz fR frequency is used for all chan-
nels. The TCXO frequency is buffered and then fed
out of U801 again on pin 14 to the voltage multiplier
and second injection circuits. The stability of the
TCXO frequency determines the stability of the
transmit and receive signals.
The fV input is produced by dividing the VCO
frequency using prescaler U800 and the N counter in
U801. As described in Figure 6.2.5, the prescaler
divides by 128 or 129. This divide number is
controlled by the N and A counters as follows:
Both the N and A counters begin counting down
from the number that they were programmed with.
When the A counter reaches zero, it halts until the N
counter reaches zero. Both counters then reset and the
cycle is repeated. The A counter is always
programmed with a smaller number than the N
counter. While the A counter is counting down, the
modulus control output to the prescaler (pin 12) is low
and the prescaler divides by 129. Then when the A
counter is halted, the modulus control output is high
and the prescaler divides by 128.
To illustrate the operation of the prescaler, N, and
A counters, a example will be used. Assume a transmit
frequency of 813.4875 (800 MHz channel 300) is
selected. Since the VCO oscillates on the transmit
frequency in the transmit mode, this is the frequency
that must be produced by the VCO. To produce this
frequency, the N and A counters are programmed as
follows:
N = 508 A = 55
To determine the overall divide number of the
prescaler, the number of input pulses required to
produce one N counter output pulse can be counted. In
this example, the prescaler divides by 129 for 129 x 55
or 7095 input pulses. It then divides by 128 for 128 x
(508 - 55) or 57,984 input pulses. The overall divide
number K is therefore 57,984 + 7095 or 65,079. The
VCO frequency of 813.4875 MHz divided by 65,079
equals 12.5 kHz which is equal to the fR input to the
phase detector.
The overall divide number K can also be deter-
mined by the following formula:
K = 128N + A
Where: N = N counter divide number
A = A counter divide number
NOTE: The formula for determining the N and A
counter divide numbers is described in Section 7.2.5.
6.2.7 LOCK DETECT (Q808, Q809)
When the synthesizer is locked on frequency, the
lock detect output on U801, pin 7 is basically a high
voltage because only very narrow negative-going
pulses are present. If the synthesizer is out-of-lock, the
negative-going pulses widen as the difference between
fR and fV increases.