MXP924
User’s Guide –
Dolphin Interconnect Solutions
Page 16
Technical Information
Board revision history
The following table gives a general overview of the hardware revision history.
MXP924 revision
Capabilities
MXP924-BB
•
Initial version for testing. Not available
MXP924-CC
•
Production version
PCIe Cable Port Signals
The external PCI Express SFF-8644 cable connector supports the following signals:
•
PETpN/PETnN:
PCI Express Transmitter pairs, labeled where N is the Lane number (starting with 0); “p” is the true signal
while “n” is the complement signal.
•
PERpN/PERnN:
PCI Express Receiver pairs, labeled where N is the Lane number (starting with 0); “p” is the true
signal
while “n” is the complement signal.
•
PWR: Power to support AOC and signal conditioning components within the cable assembly.
•
MGTPWR: Power supplied to the connector for cable management components that are needed while the link is not
active. This needs to be active if the subsystem has power.
•
CBLPRSNT#: Cable present detect, an active-low signal pulled-down by the cable when it is inserted into the MXP924
connector.
•
CADDR: Signal used to configure the upstream cable management device address.
•
CINT#: Signal asserted by the cable assembly to indicate a need for service via the CMI controller.
•
CMISDA: Management interface data line. Used for both initial link setup and sideband messages when used with CMI
compliant cables.
•
CMISCL: Management interface clock line. Used for both initial link setup and sideband messages when used with CMI
compliant cables.
External PCIe x4 Cable Connector Pin-Out
Column
Row 9
8
7
6
5
4
3
2
1
D
GND PETn2
PETp2
GND PETn1
PETp1 GND MGTPWR
PWR
C
GND PETn3
PETp3
GND PETn0
PETp0 GND CMISDA
CMISCL
B
GND PERn2 PERp2 GND PERn1 PERp1 GND CBLPRSNT# PWR
A
GND PERn3 PERp3 GND PERn0 PERp0 GND CINT#
CADDR
Table 8; External PCIe x4 cable Pin-Out
PCIe Cable Port Mapping
The MXP924 module has a quad SFF-8644 connector. The table below show the signal / port map.
