Digital Equipment Prioris HX590 DP, Service Maintenance Manual

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Digital PRIORIS HX590 & HX590 DP Server Utilities & Configuration
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Advanced Chipset Control
Menu Fields Settings Comments
CPU to PCI
posting Disabled
Enabled Enables or disables the CPU to PCI write buffers. When enabled, these
buffers temporarily store data between writes.
PCI to
memory
posting
Enabled
Disabled Enables or disables the PCI to DRAM write buffers. When enabled,
these buffers temporarily store data between writes.
CPU to
memory
posting Enabled
Disabled Enables or disables the CPU to DRAM write buffers. When enabled,
these buffers temporarily store data between writes.
PCI burst
write Enabled
Disabled Enables or disables PCI memory burst write cycles.
PCI arbiter
System default
Pure rotating
EISA slots
PCI slots 4-6
CPU
PCI slot 1
PCI slot 2
PCI slot 3
Selects the PCI arbiter priority scheme. Select “System Default” for
optimal setting.
Select “Pure Rotating” or a device with the highest priority, if
absolutely needed.
Latency timer
value
20
90
A0
F0 Sets the maximum number of PCI bus clocks that the PMPC can burst as
a master.
EISA to PCI
line buffer
Enabled
Disabled Enables or disables the EISA to PCI line buffer.
PCI Devices
Menu Fields Settings Comments
PCI devices,
slot 1/2/3/4/5/6
INTA, INTD,
INTB, INTC None
IRQ Selects IRQ routing.
Default latency
timer Enabled
Disabled When enabled, the device’s power up latency timer is used.
Latency
0040h Sets the device latency timer.