Chapter 3 - System Setup
PS-2000B Series User Manual
3-8
SDRAM CAS Latency Time
Designates the clock counts used, from the enabling of CAS to the start
of the burst transmission. Can be set to either [3] or [2]. Factory default
setting is [3] and strongly recommended for most users.
SDRAM Cycle Time Trans/Trc
Designates the number of SLCK's for an access cycle, i.e. the minumum
required time from when a bank is activated to the activation of an
identical bank. Settings are [7/9], [5/7] or [Auto]. Factory default setting
is [Auto] and strongly recommended for most users.
SDRAM RAS-to-CAS Delay
Designates the timing delay used between RAS and CAS strobe signals.
Settings are [2], [3], or [Auto]. Factory default setting is [Auto] and
strongly recommended for most users.
SDRAM RAS Precharge Time
Designates the pre-charge time value used, to allow RAS to accumulte its
charge before DRAM refresh. Settings are [2], [3], or [Auto]. Factory default
setting is [Auto] and strongly recommended for most users.
System BIOS Cacheable
Sets whether the System BIOS’ Cache is used or not. When the OS is set to use
this cache, the PS-B unit’s processing speed will increase. Settings available
are [Enabled] and [Disabled]. The factory setting is [Disabled] and is recom-
mended for most users.
Selecting the ADVANCED CHIPSET FEATURES menu item calls up the follow-
ing screen.
↑↓→←
:
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
Phoenix - AwardBIOS CMOS Setup Utility
Advanced Chipset Featrues
Item Help
Menu Level
SDRAM CAS Latency Time
[3]
SDRAM Cycle Time Tras/Trc
[Auto]
SDRAM RAS-to-CAS Delay
[Auto]
SDRAM RAS Precharge Time
[Auto]
System BIOS Cacheable
[Disabled]
Video BIOS Cacheable
[Disabled]
Memory Hole At 15M-16M
[Disabled]
CPU Latency Timer
[Enabled]
Delayed Transaction
[Enabled]
AGP Graphics Aperture Size
[64MB]
On-Chip Video Window Size
[64MB]
3.2.4 Advanced Chipset Features
