Zybo Z7 Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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The PL is nearly identical to a Xilinx 7-series Artix FPGA, except that it contains several dedicated ports and buses
that tightly couple it to the PS. The PL also does not contain the same configuration hardware as a typical 7-series
FPGA, and it must be configured either directly by the processor or via the JTAG port.
The PS consists of many components, including the Application Processing Unit (APU, which includes 2 Cortex-A9
processors), Advanced Microcontroller Bus Architecture (AMBA) Interconnect, DDR3 Memory controller, and
various peripheral controllers with their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed
I/O, or MIO pins). Peripheral controllers that do not have their inputs and outputs connected to MIO pins can
instead route their I/O through the PL, via the Extended-MIO (EMIO) interface. The peripheral controllers are
connected to the processors as slaves via the AMBA interconnect, and contain readable/writable control registers
that are addressable in t
he processors’ memory space. The programmable logic is also connected to the
interconnect as a slave, and designs can implement multiple cores in the FPGA fabric that each also contain
addressable control registers. Furthermore, cores implemented in the PL can trigger interrupts to the processors
and perform DMA accesses to DDR3 memory.
There are many aspects of the Zynq APSoC architecture that are beyond the scope of this document. For a
complete and thorough description, refer to the
Zynq Technical Reference manual
.
The table below depicts the external components connected to the MIO pins of the Zybo Z7. The Vivado board files
found on the
Zybo Z7 Resource Center
can be used to properly configure the PS to work with these peripherals. It
is also possible to use the example projects found on the resource center as a starting point for your own designs.
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