Digilent XC7Z020-1CLG400C Reference Manual Download Page 19

Zybo Z7 Board Reference Manual 

 

 

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USB Host/OTG 

The Zybo Z7 implements one of the two available PS USB OTG interfaces on the Zynq device. A Microchip USB3320 
USB 2.0 Transceiver Chip with an 8-bit ULPI interface is used as the PHY. The PHY features a complete HS-USB 
Physical Front-End supporting speeds of up to 480Mbs. The PHY is connected to MIO Bank 1/501, which is 
powered at 1.8V. The usb0 peripheral is used on the PS, connected through MIO[28-39]. The USB OTG interface 
can act as an embedded host or a peripheral device. The USB mode is controlled from software by manipulating 
the USB0 peripheral controller in the Zynq PS. When acting as a peripheral, the USB Micro AB connector (J10) 
should be used to connect to a USB host device, and JP1 and JP2 should not be shorted. When acting as an 
embedded host, the USB A connector (J11) should be used to connect to a USB peripheral device, and JP2 should 
be shorted while JP1 is not shorted. The Zybo Z7 should never have a peripheral device and a host device 
connected to these two connectors at the same time.

 

While in host mode, the Zybo Z7 is technic

ally an “embedded host”, because it does not provide the required 150 

µF of capacitance on VBUS required to qualify as a general purpose host. It is possible to modify the Zybo Z7 so 
that it complies with the general purpose USB host requirements by loading C71 with a 150 µF capacitor and 
shorting JP1. Only those experienced at soldering small components on PCBs should attempt this rework. Most 
USB peripheral devices will work just fine without loading C71. Whether the Zybo Z7 is configured as an embedded 
host or a general purpose host, it can provide 500 mA on the 5V VBUS line. Note that loading C71 may cause the 
Zybo Z7 to reset when booting embedded Linux while powered from the USB port, regardless of if any USB device 
is connected to the host port. This is caused by the in-rush current that C71 causes when the USB host controller is 
enabled and the VBUS power switch (IC12) is turned on. 

Note that if your project uses the USB host feature (embedded or general purpose), then the Zybo Z7 is very likely 
to consume more current than is allowed by a USB peripheral, causing it to periodically reset. When this occurs the 
PGOOD LED will quickly flicker and the DONE LED will go low, indicating the PL is no longer programmed. To 
prevent this, power the Zybo Z7 by a 5

V battery or wall adapter capable of providing more power. See section “1 

Power Supplies” for information on acceptable non

-USB power sources. 

 

10  Ethernet 

The Zybo Z7 uses a Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port for network connection. 
The PHY connects to MIO Bank 501 (1.8V) and interfaces to the Zynq-7000 AP SoC via RGMII for data and MDIO for 
management. The auxiliary interrupt (INTB) and reset (PHYRSTB) signals connect to PL pins to be accessed via 
EMIO. The connection diagram can be seen on Figure 10.1.

 

After power-up the PHY starts with Auto Negotiation enabled, advertising 10/100/1000 link speeds and full duplex. 
If there is an Ethernet-capable partner connected, the PHY automatically establishes a link with it, even with the 
Zynq not configured. 

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Summary of Contents for XC7Z020-1CLG400C

Page 1: ...their respective owners Page 1 of 31 Table of Contents Overview 3 Purchasing Options 5 Software Support 6 Zynq APSoC Architecture 6 Functional Description 9 1 Power Supplies 9 1 1 Power Input Sources...

Page 2: ...mmable Logic Reset 16 6 3 Processor Subsystem Reset 16 7 USB UART Bridge Serial Port 17 8 microSD Slot 17 9 USB Host OTG 19 10 Ethernet 19 11 HDMI 21 11 1 TMDS Signals 22 11 2 Auxiliary signals 22 12...

Page 3: ...Z7 adds several features and performance improvements To assist in migrating from the Zybo to the Zybo Z7 Digilent has created a migration guide available on the Zybo Z7 Resource Center Memory 1 GB D...

Page 4: ...ost OTG port 22 HDMI output port 7 USB Host power enable jumper 23 Ethernet port 8 Standard Pmod port 24 External power supply connector 9 User switches 25 Fan connector 5V three wire 10 User LEDs 26...

Page 5: ...0 are not available on the Zybo Z7 10 The differences between the two variants are summarized below Product Variant Zybo Z7 10 Zybo Z7 20 Zynq Part XC7Z010 1CLG400C XC7Z020 1CLG400C 1 MSPS On chip ADC...

Page 6: ...enter Zynq platforms are well suited to be embedded Linux targets and Zybo Z7 is no exception Digilent currently does not provide a Petalinux example for this product however one will be available in...

Page 7: ...eripheral controllers are connected to the processors as slaves via the AMBA interconnect and contain readable writable control registers that are addressable in the processors memory space The progra...

Page 8: ...3 12 JF4 13 JF1 14 JF9 15 JF10 MIO 501 1 8V Peripherals Pin ENET 0 USB 0 SDIO 0 16 TXCK 17 TXD0 18 TXD1 19 TXD2 20 TXD3 21 TXCTL 22 RXCK 23 RXD0 24 RXD1 25 RXD2 26 RXD3 27 RXCTL 28 DATA4 29 DIR 30 STP...

Page 9: ...n board power supplies are enabled or disabled by the power switch SW4 The power indicator LED LD13 labeled PGOOD is on when all the supply rails reach their nominal voltage 1 1 Power Input Sources Th...

Page 10: ...rent draws Even when attached to a host capable of providing more current the Zybo Z7 will limit itself to 75 A and will reset if this current is reached If you experience your project resetting indic...

Page 11: ...signal will assert enabling the 3 3V audio supply lighting up the power LED LD13 and de asserting the Power On Reset signal PS_POR_B of the Zynq Each power supply uses a soft start ramp of 1 10ms to l...

Page 12: ...e mode register to the 256 KB of internal RAM within the APU called On Chip Memory or OCM The FSBL must be wrapped up in a Zynq Boot Image in order for the BootROM to properly copy it The last thing t...

Page 13: ...h that the Zynq can boot from Documentation available from Xilinx describes how to use Xilinx SDK to program a Zynq Boot Image into a Flash device attached to the Zynq Once the Quad SPI Flash has been...

Page 14: ...groups were swapped as well These changes are transparent to the user During the whole design process the Xilinx PCB guidelines were followed Both the memory chips and the PS DDR bank are powered fro...

Page 15: ...n on this see section 10 Ethernet The OTP region also includes a factory programmed read only 128 bit random number The very lowest address range 0x00 0x0F can be read to access the random number See...

Page 16: ...ng sections 6 1 Power on Reset The Zynq PS supports external power on reset signals The power on reset is the master reset of the entire chip This signal resets every register in the device capable of...

Page 17: ...smit LED LD11 and the receive LED LD10 Signal names that imply direction are from the point of view of the DTE Data Terminal Equipment in this case the PC The FT2232HQ is also used as the controller f...

Page 18: ...rd files available on the Zybo Z7 resource center Figure 8 1 microSD slot signals Both low speed and high speed cards are supported the maximum clock frequency being 50 MHz A Class 4 card or better is...

Page 19: ...de 500 mA on the 5V VBUS line Note that loading C71 may cause the Zybo Z7 to reset when booting embedded Linux while powered from the USB port regardless of if any USB device is connected to the host...

Page 20: ...ard files Although the default power up configuration of the PHY might be enough in most applications the MDIO bus is available for management The RTL8211E VL is assigned the 5 bit address 00001 on th...

Page 21: ...DMI multiplexer configured as a simple switch This device is used to prevent displays from back powering the Zybo Z7 and otherwise has no effect on functionality The benefit this adds is to make it po...

Page 22: ...le and what resolutions are supported Only afterwards will video transmission begin Refer to VESA E DDC specifications for more information The Consumer Electronics Control or CEC is an optional proto...

Page 23: ...is specified in Table 12 2 When configured as master the direction of BCLK PBLRC and RECLRC is inverted In this mode the codec generates the proper frequencies for these clocks No matter where the clo...

Page 24: ...high output only when they are pressed Slide switches generate constant high or low inputs depending on their position Figure 13 1 Zybo Z7 GPIO The high efficiency LEDs are anode connected to the Zynq...

Page 25: ...to the space between the heat sink fins the heat sink does not contain mounting holes The fan must be attached with the label facing down towards the Zynq device in order to push the air flow in the c...

Page 26: ...15 Pcam Port The Pcam port included on the Zybo Z7 is a 15 pin 1 mm pitch zero insertion force ZIF connector designed specifically for attaching camera sensor modules to host systems The Pcam connect...

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Page 28: ...xible flat cable FFC To connect the cable to the Zybo Z7 follow these instruction Fig 15 2 depicts each step 1 Locate the Pcam connector between the two HDMI ports 2 Pull directly up on the off white...

Page 29: ...large collection of Pmod accessory boards that can attach to the Pmod ports to add ready made functions like A D s D A s motor drivers sensors and other functions See digilentinc com for more informa...

Page 30: ...de the regular VCCO dependent limits apply See Xilinx datasheets for more information The Dual Analog Digital Pmod on the Zybo Z7 differs from the rest in the routing of its traces The eight data sign...

Page 31: ...talk In applications where this is a concern the standard Pmod port should be used Another option would be to ground one of the signals and use its pair for the signal ended signal Since the High Spee...

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