Zybo Z7 Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
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The Zybo Z7 is configured to boot in Cascaded JTAG mode, which allows the PS to be accessed via the same JTAG
port as the PL. It is also possible to boot the Zybo Z7 in Independent JTAG mode by loading a jumper in JP3 and
shorting it. This will cause the PS to not be accessible from the onboard JTAG circuitry, and only the PL will be
visible in the scan chain. To access the PS over JTAG while in independent JTAG mode, users will have to route the
signals for the PJTAG peripheral over EMIO, and use an external device to communicate with it.
3
DDR3L Memory
The Zybo Z7 includes two Micron MT41K256M16HA-125 DDR3L memory components creating a single rank, 32-bit
wide interface and a total of 1 GiB (Gibi-byte, or 1,073,741,824 bytes) of capacity. The DDR3L is connected to the
hard memory controller in the Processor Subsystem (PS), as outlined in the Zynq documentation.
The PS incorporates an AXI memory port interface, a DDR controller, the associated PHY, and a dedicated I/O bank.
DDR3L memory interface speeds up to 533 MHz/1066 Mbps are supported.
Zybo Z7 was routed with 40 ohm (+/-10%) trace impedance for single-ended signals, and differential clock and
strobes set to 80 ohms (+/-10%). A feature called DCI (Digitally Controlled Impedance) is used to match the drive
strength and termination impedance of the PS pins to the trace impedance. On the memory side, each chip
calibrates its on-die termination and drive strength using a 240 ohm resistor on the ZQ pin.
Due to layout reasons, the two lower data byte groups (DQ[0-7], DQ[8-15]) were swapped. To the same effect, the
data bits inside byte groups were swapped as well. These changes are transparent to the user. During the whole
design process the Xilinx PCB guidelines were followed.
Both the memory chips and the PS DDR bank are powered from the 1.35V supply. The mid-point reference of
0.675V is created with a simple resistor divider and is available to the Zynq as external reference.
For proper operation it is essential that the PS memory controller is configured properly. Settings range from the
actual memory flavor to the board trace delays. For your convenience, the Zybo Z7 Vivado board files are available
on the
Zybo Z7 Resource Center
and automatically configure the Zynq Processing System IP core with the correct
parameters.
For best DDR3L performance, DRAM training is enabled for write leveling, read gate, and read data eye options in
the PS Configuration Tool in Xilinx tools. Training is done dynamically by the controller to account for board delays,
process variations and thermal drift. Optimum starting values for the training process are the board delays
(propagation delays) for certain memory signals.
Board delays are specified for each of the byte groups. These parameters are board-specific and were calculated
from the PCB trace length reports. The DQS to CLK Delay and Board Delay values are calculated specific to the Zybo
Z7 memory interface PCB design.
For more details on memory controller operation, refer to the Xilinx
Zynq Technical Reference manual
.
4
Quad-SPI Flash
The Zybo Z7 features a Spansion S25FL128S 4-bit Quad-SPI serial NOR flash. The key device attributes are:
•
Part number S25FL128S
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