Zybo Z7 Board Reference Manual
Copyright Digilent, Inc. All rights reserved.
Other product and company names mentioned may be trademarks of their respective owners.
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Pin/Signal
HDMI TX
HDMI RX
Description
FPGA pin
Description
FPGA pin
SCL, SDA
DDC bidirectional
(optional)
G17, G18
DDC bidirectional
W18, Y19
D[2]_P, D[2]_N
Data output
B19, A20
Data input
N20, P20
Table 11.1. HDMI pin description and assignment.
11.1 TMDS Signals
HDMI/DVI is a high-speed digital video stream interface using transition-minimized differential signaling (TMDS).
To make proper use of either of the HDMI ports, a standard-compliant transmitter or receiver needs to be
implemented in the Zynq PL. The implementation details are outside the scope of this manual. Check out the
vivado-library IP Core repository on the
Digilent github
for ready-to-use reference IP. The IP cores for transmitting
and receiving are called rgb2dvi and dvi2rgb, respectively.
11.2 Auxiliary signals
Whenever a sink is ready and wishes to announce its presence, it connects the 5V0 supply pin to the HPD pin. On
the Zybo Z7, this is done by driving the Hot Plug Assert signal high. Note this should only be done after a DDC
channel slave has been implemented in the Zynq PL and is ready to transmit display data.
The Display Data Channel, or DDC, is a collection of protocols that enable communication between the display
(sink) and graphics adapter (source). The DDC2B variant is based on I2C, the bus master being the source and the
bus slave the sink. When a source detects high level on the HPD pin, it queries the sink over the DDC bus for video
capabilities. It determines whether the sink is DVI or HDMI-capable and what resolutions are supported. Only
afterwards will video transmission begin. Refer to VESA E-DDC specifications for more information.
The Consumer Electronics Control, or CEC, is an optional protocol that allows control messages to be passed
around on an HDMI chain between different products. A common use case is a TV passing control messages
originating from a universal remote to a DVR or satellite receiver. It is a one-wire protocol at 3.3V level connected
to a Zynq PL user I/O pin. The wire can be controlled in an open-drain fashion allowing for multiple devices sharing
a common CEC wire. Refer to the CEC addendum of HDMI 1.3 or later specifications for more information.
12 Audio
An Analog Devices SSM2603 Audio Codec provides integrated digital audio processing to the Zynq-7000 AP SoC. It
allows for stereo record and playback at sample rates from 8 kHz to 96 kHz.
On the analog side, the codec connects to three 3.5 mm standard audio jacks. There are two inputs: a mono
microphone and a stereo line in. There is one stereo output, the headphone jack. Analog power is provided by a
dedicated linear power supply (IC5).
Audio Jack
Description
Channels
Color
J5
Headphone Out
Stereo
Black
J6
Microphone In
Mono
Pink
J7
Line In
Stereo
Light Blue
Table 12.1. Analog audio signals.
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