Digi NS7520B Series Hardware Reference Manual Download

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S e r i a l C h a n n e l r e g i s t e r s

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Summary of Contents for NS7520B Series

Page 1: ...Part number version 90000353_G Release date September 2007 www digiembedded com NS7520 Hardware Reference...

Page 2: ...change without notice and does not represent a committment on the part of Digi International Digi provides this document as is without warranty of any kind either expressed or implied including but no...

Page 3: ...rk software suite Conventions used in this guide This table describes the typographic conventions used in this guide This convention Is used for italic type Emphasis new terms variables and document t...

Page 4: ...port Be aware that if you see differences between the documentation you received in your package and the documentation on the Web site the Web site content is the latest version Support To get help wi...

Page 5: ...kaging 8 Pinout detail tables and signal descriptions 11 System bus interface 12 Chip select controller 16 Ethernet interface MAC 18 No connect pins 21 General purpose I O 21 System clock and reset 24...

Page 6: ...k generation NS7520 clock module 49 External oscillator vs internal PLL circuit 49 NS7520 clock module block diagram 50 Using the external oscillator 50 External oscillator mode hardware configuration...

Page 7: ...the chip select address range 88 Memory Module Configuration register 89 Chip Select Base Address register 92 Chip Select Option Register A 97 Chip Select Option Register B 101 Static memory SRAM con...

Page 8: ...onsiderations 144 Ethernet transmitter considerations 145 Ethernet receiver considerations 145 External peripheral DMA support 146 Signal description 147 External DMA configuration 147 Memory to memor...

Page 9: ...nd register 191 MII Management Address register 192 MII Management Write Data register 193 MII Management Read Data register 194 MII Management Indicators register 195 SMII Status register 196 Station...

Page 10: ...lup and pulldown characteristics 259 Absolute maximum ratings 261 AC characteristics 261 AC electrical specifications 261 Oscillator Characteristics 263 Timing Diagrams 265 Timing_Specifications 265 R...

Page 11: ...309 Erroneous timeouts when loading timer 309 Station Address Logic Multicast and broadcast packet filtering 310 Station Address Logic Unicast packets 310 Corrupt Ethernet receive packets 311 Transmi...

Page 12: ...xii...

Page 13: ...esigned for use in intelligent networked devices and Internet appliances The NS7520 is based on the standard architecture in the NET ARM family of devices NET ARM is the hardware foundation of the NET...

Page 14: ...timers 13 channel DMA controller External bus expansion module 16 general purpose I O GPIO pins Key features and operating modes of the major NS7520 modules CPU core ARM7 32 bit RISC processor 32 bit...

Page 15: ...erator external clock for synchronous operation Receive side character and buffer gap timers Four receive side data match detectors Power and operating voltages 500 mW maximum at 55 MHz all outputs sw...

Page 16: ...a range of operating frequencies from 10 to fMAX Maximum operating frequency from external clock or using PLL multiplication fMAX Bus interface Five independent programmable chip selects with 256 Mb...

Page 17: ...ebugger PLL System Clock JTAG Debug Interface ARM7TDMI FIRQ IRQ 2 timers Watchdog timer Power 3 3V 1 5V BBUS D M A D M A D M A D M A Serial A UART SPI Serial B UART SPI 4 level interrupt inputs 16 GPI...

Page 18: ...36 MHz 46 MHz and 55 MHz The operating frequency is set during bootstrap initialization using pins A 8 0 These address pins load the PLL settings register on powerup reset A 8 7 determines IS charge p...

Page 19: ...vironment requiring networking services in an Ethernet LAN The NS7520 contains an integrated ARM RISC processor 10 100 Ethernet MAC serial ports memory controllers and parallel I O The NS7520 can inte...

Page 20: ...e 1 provides the NS7520 packaging dimensions Figure 2 shows the pinout and NS7520 dimensions Figure 3 shows the NS7520 BGA layout Symbol Min Nom Max A 1 4 A1 0 35 0 40 0 45 A2 0 95 b 0 45 0 50 0 55 D...

Page 21: ...w w w d i g i e m b e d d e d c o m 9 P i n o u t a n d P a c k a g i n g Figure 2 NS7520 pinout and dimensions 177 PFBGA...

Page 22: ...Y14 8 XTALB2 A11 N7 H15 D12 A0 F14 B4 OSCVCC1 RXD2 PORTA4 A4 C1 D11 P14 CS3_ BISTEN_ D13 J3 P2 GNDPY13 13 PORTA7 C13 F1 L3 G12 A5 D7 P3 B3 VCCPY9 E 3 L14 G A15 BE2_ B10 H12 N4 A18 VDDC04 D4 D3 A3 G14...

Page 23: ...at the pin is a pullup resistor input current source D next to the pin number indicates that the pin is a pulldown resistor input current sink No value next to the pin indicates that the pin has neith...

Page 24: ...CS0_ and OE_ ADDR26 CS0WE_ P10 U I O 4 Addr bit 26 Logical AND of CS0_ and WE_ External bus External bus ADDR25 M10 U I O 4 Remainder of address bus through ADDR0 ADDR24 R10 U I O 4 ADDR23 N9 U I O 4...

Page 25: ...DATA31 N1 I O 4 Data bus DATA30 M1 I O 4 DATA29 L3 I O 4 DATA28 L2 I O 4 DATA27 L4 I O 4 DATA26 L1 I O 4 DATA25 K3 I O 4 DATA24 K2 I O 4 DATA23 K1 I O 4 DATA22 J2 I O 4 DATA21 J3 I O 4 DATA20 J1 I O 4...

Page 26: ...e enable D07 D00 TS_ A8 U I O 4 DO NOT USE Add an external 820 ohm pullup to 3 3 V TA_ D8 U I O 4 Data transfer acknowledge Add an external 820 ohm pullup to 3 3 V TA_ is bidirectional It is used in i...

Page 27: ...commendation Less than x32 S DRAM SRAM memory configurations Unconnected data bus pins will float during memory read cycles Floating inputs can be a source of wasted power For other than x32 DRAM SRAM...

Page 28: ...i directional The NS7520 or the external peripheral can drive this signal RW_ Read write indicator Indicates the direction of the system bus memory cycle RW_ high indicates a read operation RW_ low in...

Page 29: ...indicate the end of the current memory cycle For FP EDO DRAM these signals provide the RAS signal CAS0_ CAS1_ CAS2_ CAS3_ Column address strobe signals Activated when an address is decoded by a chip...

Page 30: ...one of the chip selects in the memory module Mnemonic Signal Description Table 5 Chip select controller signal description Symbol Pin I O OD Description MII ENDEC MII ENDEC MDC GP output D10 O 2 MII...

Page 31: ...in Table 69 MII Management Configuration register bit definition on page 189 MDIO Management data IO A bi directional signal that provides a serial data channel between the NS7520 and the external Eth...

Page 32: ...le The receive clock provides the synchronous data clock for receive data RXD3 RXD2 RXD1 RXD0 Receive data signals Nibble bus used by the NS7520 to input receive data from the external Ethernet PHY Al...

Page 33: ...alue 10 20K ohms is acceptable P12 Add a 15K ohm pulldown to GND 15K ohm is the recommended value 10 20K ohms is acceptable N12 Tie to GND R15 XTALB2 NO CONNECT M11 NO CONNECT P11 NO CONNECT N11 NO CO...

Page 34: ...hannel 1 DCD Channel 1 SPI enable SEL_ Channel 1 TXCLK DMAchannel3 5 DONE_In PORTC7 TXDB G13 U I O 2 Channel 2 TXD GEN interrupt out PORTC6 DTRB_ DREQ2_ G14 U I O 2 Channel 2 DTR_ DMAchannel4 6 Req PO...

Page 35: ...RTC 3 0 pins provide level sensitive interrupts The inputs do not need to be synchronous to any clock The interrupt remains active until cleared by a change in the input signal level Signal descriptio...

Page 36: ...p resources Symbol Pin I O OD Description XTALA1 K14 I ARM system oscillator circuit XTALA2 K12 O PLLVDD 1 5V L15 P PLL clean power PLLVSS L12 P PLL return RESET_ A10 I System reset Table 10 System cl...

Page 37: ...t operations See Chapter 5 SYS Module for more information tR max 18ns Vin 0 8Vto 2 0V tF max 18ns Vin 2 0Vto 0 8V tF tR Symbol Pin I O OD Description PLLTST_ N15 I Encoded with BISTEN_ and SCANEN_ Ad...

Page 38: ...e termination circuit on the development PCB TCK P15 I Test mode clock Add an external pullup to 3 3V Table 13 JTAG test pinout Mnemonic Signal Description TDI Test data in TDI operates the JTAG stand...

Page 39: ...cations for use in boundary scan testing These signals meet the requirements of the Raven and Jeeni debuggers TCK Test mode clock TCK operates the JTAG standard Consult the JTAG specifications for use...

Page 40: ...lectrical specifications in Chapter 11 Electrical Characteristics for more information Signal Pin Description Oscillator VCC 3 3V N13 C3 Oscillator power supply Core VCC 1 5V R8 L14 C14 C13 Core power...

Page 41: ...orking with the CPU C H A P T E R 3 The CPU uses an ARM7TDMI core processor which provides high performance while maintaining low power consumption and small size This chapter describes the ARM Thumb...

Page 42: ...iled in ARM mode Thumb instructions operate with the standard ARM register configuration allowing interoperability between ARM and Thumb states Each 16 bit Thumb instruction has a corresponding 32 bit...

Page 43: ...some state information then jump to a location in low memory referred to as the vector table see Exception vector table on page 33 Before an exception can be handled the current processor state must b...

Page 44: ...t a specific supervisor instruction Abort exception An abort exception indicates that the current memory access cannot be completed There are two types of abort exception Prefetch Occurs during an ins...

Page 45: ...hat the transfer error does not escape detection The time for this exception entry should be added to worst case FIRQ latency calculations Exception vector table All exceptions result in the ARM proce...

Page 46: ...the IRQ interrupt Firmware sets the priorities for servicing interrupts at bootup using the bits defined in the Interrupt Status register Detail of ARM exceptions Reset exception A reset exception is...

Page 47: ...s of abort exception Prefetch abort Occurs during an instruction prefetch If a prefetch abort occurs the prefetch instruction is marked as invalid but the exception is not taken until the instruction...

Page 48: ...interrupt sourced by the ARM7TDMI interrupt controller IRQ has a lower priority than FIRQ and is masked out when an FIRQ sequence is entered IRQ can be disabled at any time by setting the I bit in CP...

Page 49: ...exception The exception handler does not need to determine from which state the exception was entered With an SWI for example MOVS PC R14_SVC always returns to the next instruction whether executed i...

Page 50: ...e prefetch abort BL is a branch with link instruction 2 Where PC is the address of the instruction that was not executed since FIRQ or IRQ took priority 3 Where PC is the address of the load or store...

Page 51: ...controlled using the Timer Control registers hFFB0 0010 18 The corresponding bit in the Interrupt Enable register must be set for either IRQ or FIRQ to function The watchdog timer is controlled using...

Page 52: ...iver have five possible interrupt sources See Chapter 8 DMA Module Ethernet receive and transmit interrupts There are three interrupts for Ethernet receive and four interrupts for Ethernet transmit al...

Page 53: ...W o r k i n g w i t h t h e C P U PORTC interrupts The lower four pins of PORTC C3 C2 C1 C0 on the ARM7TDMI can be used as interrupt sources Only the PORTC register enables configures and services th...

Page 54: ...H a r d w a r e I n t e r r u p t s 4 2 N S 7 5 2 0 H a r d w a r e R e f e r e n c e R e v G 9 2 0 0 7...

Page 55: ...escribes the BBus module which provides the data path between NS7520 internal modules Additional BBus functionality includes Address and multiplexing logic that supports the data flow through the NS75...

Page 56: ...ignals Once mastership is granted the targeted device is selected Table 19 illustrates bus master and slave modules Cycles and BBus arbitration During a normal cycle each bus master cycle is allowed o...

Page 57: ...nternal module is given 1 Mbyte of address space for its own internal decoding Each module defines its own specific register map The BBus module does not allow access to any internal registers unless...

Page 58: ...A d d r e s s d e c o d i n g 4 6 N S 7 5 2 0 H a r d w a r e R e f e r e n c e R e v G 9 2 0 0 7...

Page 59: ...w w w d i g i e m b e d d e d c o m 47 S Y S M o d u l e SYS Module C H A P T E R 5 The SYS module provides the NS7520 with its system clock SYS_CLK and system reset SYS_RESET resources...

Page 60: ...that shares pins with the TAP controller used for 1149 1 JTAG boundary scan testing To enable the ARM7TDMI TAP Signal mnemonic Signal name Description XTALA1 XTALA2 Clock source Operate in one of two...

Page 61: ...the timing for the DRAM refresh counter can be selected instead of BCLK to provide timing for the watchdog timer the two internal timers and the Serial module External oscillator vs internal PLL circ...

Page 62: ...ivided by five For example with a 55MHz oscillator BCLK would be 55 MHZ and FXTAL would be 11MHz Note Using an external oscillator with PLL enabled is not advantageous due to the PLL input limitation...

Page 63: ...esistor The SCANEN input is tied to 3 3 volts through a 10K resistor This diagram shows the hardware configuration Using the PLL circuit The NS7520 can use its PLL external oscillator to generate the...

Page 64: ...quency For normal debug mode this jumper is removed The BISTEN input is tied to 3 3 volts through a 10K resistor The SCANEN input is pulled high to 3 3V through a 10K resistor A two position jumper is...

Page 65: ...TAL XTALA1 K14 XTALA2 K12 1 5V A0 A1 A2 A3 A4 A5 A6 A7 A8 The NS7520 address bus has internal pullups 2 7K pulldown resistors can be connected to the address lines to configure the PLL settings at boo...

Page 66: ...rnal pullups The normally high values can be changed to 0 by connecting 2 7K pulldown resistors 2 The PLL Settings register is configured by writing to the PLL Control register Only the ND field can b...

Page 67: ...d only FS b00 Output divider Sets the PLL s output divider The FS field defaults to b00 when address lines 6 5 are not pulled down on powerup This is the correct setting for all frequencies and should...

Page 68: ...0010E 73 7 11 11 11 00 11011 10000 0x0000010F 78 3 10 11 11 00 00100 10001 0X00000190 82 9 10 11 11 00 00101 10010 0x00000191 87 6 10 11 11 00 00110 10011 0x00000192 92 2 10 11 11 00 00111 10100 0x000...

Page 69: ...ing to the PLL Control register FFB0 0008 The PLL frequency can be changed by writing to the PLLCNT field in the PLL Control register At bootup the default value in the PLLCNT field has no affect on t...

Page 70: ...gured on bootup The IS field is b10 for all standard frequencies from 36 9MHz to 55 3MHz The ND field can be changed to 16 different values based on the PLLCNT The next table shows the 16 frequencies...

Page 71: ...t up At other times RESET_ must be one microsecond minimum Watchdog reset The watchdog reset is synchronous to SYS_CLK A hardware reset condition is triggered when the signal transitions from active t...

Page 72: ...dian configuration 0 Little Endian configuration 1 Big Endian configuration ADDR 26 CPU bootstrap 0 CPU disabled GEN_BUSER 1 1 CPU enabled GEN_BUSER 0 ADDR 24 23 CS0 MMCR 19 18 setting 00 8 bit SRAM 6...

Page 73: ...C H A P T E R 6 The GEN module provides the NS7520 with its main system control functions as well as the following Two programmable timers with interrupt One programmable bus error timer One programma...

Page 74: ...ization on page 59 Address Register FFB0 0000 System Control register FFB0 0004 System Status register FFB0 000C Software Service register FFB0 0010 Timer 1 Control register FFB0 0014 Timer 1 Status r...

Page 75: ...gures the chip to operate in Little Endian mode 0 Configures the chip for Big Endian mode D30 29 N A Reserved N A Initialized to and always read as 10 full speed D28 R W BCLKD 0 BCLK output disable 0...

Page 76: ...1 Reserved D21 20 R W SWT 0 Software watchdog timeout in seconds Controls the timeout period for the watchdog timer The timeout period is a function of FXTALE 00 220 FXTALE 01 222 FXTALE 10 224 FXTALE...

Page 77: ...egisters in CPU user mode Controls whether applications operating in ARM user mode rather than supervisor mode can access internal registers within the NS7520 If set to 0 and an application operating...

Page 78: ...error on misaligned cycles 0 Disable misaligned data transfer bus abort generation 1 Generate a bus abort during a misaligned transfer When this bit is set to 1 misaligned address transfers cause a d...

Page 79: ...Do not use this setting The NS7520 can process the TA_ input signal using a 1 stage flip flop synchronizer or a 2 stage synchronizer A 1 or 2 stage synchronizer must be used when TA_ input is asynchr...

Page 80: ...ion D31 24 R O REV h29 NS7520 revision ID Provides hardware identification of the NS7520 and its revision Current NS7520 device and revision ID is REV field h29 D23 R C EXT N A Last reset caused by ex...

Page 81: ...serted this reset does not initialize internal parameters as described in NS7520 bootstrap initialization on page 59 PLL is set reset during every reset condition Clear this bit by writing hF in bits...

Page 82: ...must be in supervisor mode for the second operation Register bit assignment Timer Control registers Address FFB0 0010 FFB0 0018 Timers 1 and 2 provide the CPU with programmable interval timer s The t...

Page 83: ...terrupt is generated when the hardware sets the TIP bit in the Timer Status register see Timer Status registers on page 73 D29 R W TIRO 0 Timer interrupt mode 0 Normal interrupt 1 Fast interrupt Contr...

Page 84: ...se FXTALE as timer clock source 1 Use FSYSCLK as timer clock source Selects the reference clock for the timer module D26 00 R W ITC 0 Initial timer count Defines the TIMEOUT parameter for interrupt fr...

Page 85: ...bit Note TIP is set immediately when the TE bit in the Timer Control register is changed from 0 to 1 An interrupt occurs immediately after TE transitions from 0 to 1 If this initial interrupt causes a...

Page 86: ...Description D31 24 R W AMODE 0 PORTA mode configuration 0 Selects GPIO mode 1 Selects special function mode Configures the individual PORTA pins Each bit in the AMODE field corresponds to one of the...

Page 87: ...A field defines the current state of the GPIO signal when the signal is defined to operate in GPIO output mode Writing the ADATA field when configured in GPIO input mode or special function mode has n...

Page 88: ...eads data from the register whose data drives the pin This can for example mask a short circuit on the output pin All other configurations Reads the state of the pin PORTA4 When PORTA4 is configured w...

Page 89: ...ODE h10 PORTC mode Configures the individual PORTC pins Each bit in the CMODE field corresponds to one of the PORTC bits D31 controls PORTC7 D30 controls PORTC6 and so on D23 16 R W CDIR h10 PORTC dat...

Page 90: ...ess of its configuration mode Writing the CDATA field defines the current state of the GPIO signal when the signal is defined to operate in GPIO output mode Writing the CDATA field when configured in...

Page 91: ...e driver for that pin There should be no external driver on a pin configured for output PORTC0 GPIO IN GPIO OUT LEVELIRQ0 CDIR0 PORTC bit CSF 1 CMODE 0 CMODE 1 CDIR 0 CDIR 1 CDIR 0 CDIR 1 PORTC7 SER2_...

Page 92: ...0 1 CDIR 0 1 the configuration of Serial Channel B determines the function SER2_SPI_M_ENABLE_OUT or SER2_OUT2 PORTC 3 0 These pins can be programmed individually to generate level sensitive interrupts...

Page 93: ...g on whether a register is read or written When read the register indicates the current state of all enabled interrupts When written a 1 in a bit position sets that interrupt enable a 0 in a bit posit...

Page 94: ...TX 0 The SER 2 TX bit position corresponds to an interrupt sourced by the Serial Channel B transmitter D11 08 N A Reserved N A N A D07 R W MAC1 0 The MAC1 bit position corresponds to an interrupt sou...

Page 95: ...w w w d i g i e m b e d d e d c o m 83 G E N M o d u l e...

Page 96: ...I n t e r r u p t s 8 4 N S 7 5 2 0 H a r d w a r e R e f e r e n c e R e v G 9 2 0 0 7...

Page 97: ...o d u l e Memory Controller Module C H A P T E R 7 The memory MEM module provides a glueless interface to external memory devices such as flash DRAM and EEPROM The memory controller contains an integr...

Page 98: ...ny NS7520 configuration features are application specific and need to be configured at powerup before the CPU boots See NS7520 bootstrap initialization on page 59 PORTA2 the DRAM address multiplexer p...

Page 99: ...module can be programmed to drive a multiplexed address on A 13 0 and drives the remainder of the address from the current bus master to A 27 14 The CS 4 0 _ signals provide the CS 4 0 _ function The...

Page 100: ...coding process Address Mnemonic Register FFC0 0000 MMCR Memory Module Configuration register FFC0 0010 BAR0 Chip Select 0 Base Address register FFC0 0014 OR0A Chip Select 0 Option Register A FFC0 0018...

Page 101: ...ogical AND function is the equal to operator The NS7520 supports only 28 address bits Each chip select is limited to 256 Mbytes Memory Space The MASK field can alias a memory location in different are...

Page 102: ...te There is a small performance and power penalty for programming a refresh period smaller than required The memory controller generates CAS before RAS refresh cycles for all DRAM types D23 R W REFEN...

Page 103: ...n external DRAM multiplexer The RAS CAS address select signal is routed out the PORTA2 signal The external DRAM RAS CAS multiplexer uses the PORTA2 signals to determine when to switch the address mult...

Page 104: ...s referenced from address instead of chip select The NS7520 provides the address signals during the earliest part of each memory cycle The CS0OE_ and CS0WE_ signals are connected to the OE_ and WE_ in...

Page 105: ...field is set to h00200 When accessing a static memory device the maximum value of the base address is 0x03000000 See Setting the chip select address range on page 88 for more information D11 10 R W PG...

Page 106: ...peripheral 1 indicates that an external DRAM multiplexer is to be used for this chip select where PORTA2 determines when the external multiplexer switches the address bits When the PORTA2 signal is ac...

Page 107: ...perate in DRAM mode WE CTRL and OE CTRL bits are ignored in DRAM mode they are used only when DRSEL is set to 0 D02 R W BURST 0 Burst memory cycle enable Controls whether the memory peripheral device...

Page 108: ...ler uses the fields in the Chip Select Base Address and Chip Select Option registers to control the behavior of the peripheral memory cycles Note It is important that you set the V bit last after all...

Page 109: ...1 08 R W WAIT 3 0 0 for CS 4 1 b1111 for CS0 Memory timing control fields The WAIT field controls the number of wait states for all single cycle memory transfers and the first memory cycle of a burst...

Page 110: ...one BCLK cycle CAS_ is asserted for WAIT 5 BCLK cycles in a single access CAS_ is negated for one clock cycle between assertions If WAIT is set to 0 the controller behaves as if WAIT is set to 1 The f...

Page 111: ...ess Controls the maximum number of memory cycles that can occur in a burst cycle This field determines only the maximum number of allowable bus cycles the current bus master can choose to burst a smal...

Page 112: ...to 1 during burst operation there are no transitions on CS 4 0 or OE_ between single transfers with a burst D00 R W WE CTRL_ 0 Write cycle mode 0 Operate in WE controlled mode the memory peripheral o...

Page 113: ...t Option Register A and the two WAIT bits in this register The BCYC field controls the number of clock cycles for the secondary portion of a burst cycle The complete BCYC field is the concatenation of...

Page 114: ...s that can use BCLK or CS 4 0 _ as the data transfer signal Figure 6 shows synchronous SRAM cycles D01 00 R W SYNC 0 TA_ input synchronizer 00 Reserved 01 1 stage synchronizer 10 2 stage synchronizer...

Page 115: ...falling edge after CS 4 0 _ is deasserted The rising edge of BCLK where TA_ is low defines the end of the memory cycle referred to as the T2 state During synchronous read cycles read data is sampled o...

Page 116: ...BE_ OE_ or WE_ signal transitions high on the first falling edge after TA_ is recognized TA_ is sampled using the rising edge of BCLK The rising edge of BCLK where TA_ is low defines the last TW cycle...

Page 117: ...the DMUXS bit in the Chip Select Base Address register determines which multiplexer is used Using the internal multiplexer When configured to use the internal address multiplexer the DRAM address sign...

Page 118: ...RAS and CAS timeframes Table 40 applies to Mode 0 Table 41 applies to Mode 1 The top row of the table identifies the physical address connection on the NS7520 devices The DRAM row identifies the phys...

Page 119: ...0 9 8 7 6 5 4 3 2 1 16 bit DRAM peripheral 20 address bits 10 RAS and 10 CAS NS7520 pin A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 DRAM pin A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RAS 20 19 18 17 16 15 14 13...

Page 120: ...AMUX is set the NS7520 drives the address bus using standard addressing without any multiplexing the internal multiplexer is disabled and the multiplexer indicator is driven out the PORTA2 pin The AMU...

Page 121: ...riven active low DRAM refresh The NS7520 MEM module executes a refresh cycle that supports Fast Page FP EDO and SDRAM devices The FP and EDO devices are refreshed using the CAS before RAS technique SD...

Page 122: ...All DRAM cycles must operate a minimum of 1 wait state If the controller is programmed for 0 wait states operation is unpredictable A single wait state DRAM cycle requires the DRAM devices to tolerat...

Page 123: ...hen bursting at full bus speed with EDO write timing is controlled by a combination of BCYC and WAIT otherwise BCYC controls the length of subsequent burst cycles See Chip Select Option Register A beg...

Page 124: ...ion Using two x16 SDARM components referred to as Device 1 and Device 2 Using one x32 SDRAM component In the 2Mx32 SDRAM configuration bank selects BA0 and BA1 are not connected in numerical order The...

Page 125: ...A2 A0 A0 A0 A0 A3 A1 A1 A1 A1 A4 A2 A2 A2 A2 A5 A3 A3 A3 A3 A6 A4 A4 A4 A4 A7 A5 A5 A5 A5 A8 A6 A6 A6 A6 A9 A7 A7 A7 A7 A10 A8 A8 A8 A8 A11 A9 A9 A9 A9 A12 A13 A11 A11 A21 BA BA1 A22 BA0 BA0 BA0 A23...

Page 126: ...RAM signal CS RAS_ CS 4 0 _ CS 4 0 _ CAS3_ RAS_ RAS_ CAS2_ CAS_ CAS_ CAS1_ WE_ WE_ CAS0_ A10 AP A10 AP BE3_ UDQM_ UDQM_ BE2_ LDQM_ LDQM_ BE1_ N A N A BE0_ N A N A A1 A0 A0 A2 A1 A1 A3 A2 A2 A4 A3 A3 A...

Page 127: ...typically is constructed using one x8 SDRAM component A22 BA1 BCLK CLK CLK VCC CKE CKE D31 D16 D15 D00 D15 D00 NS7520 signal 16M SDRAM signal 64M SDRAM signal CS RAS_ CS 4 0 _ CS 4 0 _ CAS3_ RAS_ RAS_...

Page 128: ...ead and write commands the AP signal provides the auto precharge command indicator The NS7520 drives 0 during read and write commands During the precharge command the A10 AP signal indicates whether a...

Page 129: ...matic precharge should not be performed During the precharge command the NS7520 drives a 1 on the CAS0_ pin indicating that all banks should be precharged Command definitions SDRAMs operate according...

Page 130: ...can be issued The BCYC configuration in the Chip Select Option register provides the SDRAM CAS latency parameter The BCYC field must be set to a value of CAS latency 1 The NS7520 can support SDRAMs th...

Page 131: ...he SDRAM Control register The load mode command is executed only on the first memory cycle following power reset SDRAM Mode register The SDRAM Mode register is loaded during the first memory cycle to...

Page 132: ...de timing examples for SDRAM normal and burst reads respectively with WAIT and BCYC configured with a value of 0 Figure 11 SDRAM normal read One Valid Per Cycle precharge activate read bstop BCLK TS_...

Page 133: ...tive command depending on the WAIT configuration The active command is always issued after the precharge command and selects a newly activated row address Additional clock cycles are inserted between...

Page 134: ...issued The number of cycles is calculated as CAS latency 1 When the CAS latency value is greater than one additional wait states are inserted between T2 and the next system bus cycle to account for t...

Page 135: ...he last row accessed Additional clock cycles are inserted between the precharge command and the active command depending on the WAIT configuration The active command is always issued after the prechar...

Page 136: ...he number of bus cycles for the burst cycle reached the maximum as defined in the BSIZE field of the Chip Select Option register The current memory address has reached a 64 byte page boundary The bus...

Page 137: ...at address offset hC The peripheral however has trouble providing the value at h10 The NS7520 is operating with the BCYC burst timing and the memory peripheral needs an access cycle using the WAIT ti...

Page 138: ...P e r i p h e r a l p a g e b u r s t s i z e 1 2 6 N S 7 5 2 0 H a r d w a r e R e f e r e n c e R e v G 9 2 0 0 7...

Page 139: ...locks of data between memory and a memory peripheral Each block transfer is defined by a descriptor of two words memory to peripheral or three words memory to memory in circular buffers maintained by...

Page 140: ...ck diagram The DMA controller arbiter determines which channel the state machine currently is operating Fly by operation transfers There are two modes of fly by operation Read mode Transfers data from...

Page 141: ...transfers Memory to memory operation When configured for memory to memory read to write operations the DMA controller uses a temporary holding register between read and write operations Two memory cyc...

Page 142: ...er descriptors are located in 1024 byte circular buffers The first buffer descriptor address is provided by the DMA channel s buffer descriptor pointer Subsequent buffer descriptors follow the first d...

Page 143: ...annel L When set tells the DMA controller that this buffer descriptor is the last descriptor and completes an entire message frame The DMA controller uses this bit to signal the peripheral Use this bi...

Page 144: ...eive buffer pointed to by the source buffer pointer After filling the receive buffer with peripheral data the DMA controller updates this field with the actual receive data byte count Buffer length Me...

Page 145: ...ess otherwise noted Address map The next table sows the address map for the DMA channel configuration registers Channel Base address DMA channel peripheral Fly by mode 1 hFF90 0000 Ethernet port 1 rec...

Page 146: ...ister FF90 0050 DMA 1 C Control register FF90 0054 DMA 1 C Status register FF90 0060 DMA 1 D Buffer Descriptor Pointer register FF90 0070 DMA 1 D Control register FF90 0074 DMA 1 D Status register FF9...

Page 147: ...gister FF90 0170 DMA 9 Control register FF90 0174 DMA 9 Status register FF90 0180 DMA 10 Buffer Descriptor Pointer register FF90 0190 DMA 10 Control register FF90 0194 DMA 10 Status register FF90 01A0...

Page 148: ...e This feature allows the Ethernet receiver to choose the optimum buffer size for the incoming packet DMA Control register Address FF90 0010 30 50 70 90 B0 D0 F0 110 130 150 170 190 1B0 1D0 1F0 Regist...

Page 149: ...the bus 00 100 no limit The DMA channel can arbitrate each time 01 100 no limit The DMA channel can arbitrate each time 10 50 The DMA channel can arbitrate 2 out of 4 times 11 50 The DMA channel can...

Page 150: ...d size is always 32 bits When performing DMA to an external peripheral the size field determines the operand size The DMA controller moves information using burst cycles If the attached memory periphe...

Page 151: ...aries a size of 16 or 8 bits is required If the starting source or destination boundaries are on odd byte boundaries a size of 8 bits is required D23 R W REQ 0 Channel request source 0 Internal periph...

Page 152: ...rce address pointer Controls whether the source address pointer is incremented after each DMA transfer The DMA controller uses this bit in all modes when referring to a memory address This bit is igno...

Page 153: ...channel state shown in binary 000000 IDLE 000001 Load source buffer address 000100 Load destination buffer address 001000 First operand 010000 Memory to memory second operand 100000 Update buffer des...

Page 154: ...the IDONE bit is active in the current buffer descriptor A normal DMA channel completion occurs when the BLEN count expires gets to 0 or when a peripheral device signals completion D30 R C ECIP 0 Erro...

Page 155: ...to the next buffer descriptor when CAIP is cleared The CA bit in the DMA Control register must be cleared using firmware before CAIP is cleared Otherwise the next buffer descriptor aborts as well D27...

Page 156: ...R W CAIE 0 Channel abort interrupt enable Use these bits to enable interrupts to be generated when the associated IP bits are set In general the NCIE bit is used for inbound write DMA operations The D...

Page 157: ...to 1 in the DMA Control register The transmit DMA now starts again at the beginning The recovery is implemented in the NET OS BSP no data is lost and there is no other effect on operation Ethernet tra...

Page 158: ...register you must use this procedure to guarantee successful operation 1 Set the ERXDMA in the Ethernet General Control register to zero 2 SET the ERX bit in the Ethernet General Control register to...

Page 159: ...nsfers Signal Description DREQ_ An input to the NS7520 sourced by the external device All transfers are initiated when the external device asserts DREQ_ low When the external device wants a DMA transf...

Page 160: ...nction with appropriate memory device timing or external bus cycle timing accepts data when DACK_ is asserted TEA_ indicates the existence and termination of burst cycles DMA controller reset You can...

Page 161: ...th one IEEE 802 3u compatible Ethernet interface Two modules comprise the Ethernet interface the Ethernet front end EFE and the media access controller MAC The MAC module interfaces to an external phy...

Page 162: ...e EFE module provides the FIFO handling interface between the NS7520 BBus and MAC modules Figure 21 Ethernet front end module Basic features in the EFE include Control and status registers for MAC tra...

Page 163: ...ultiple times from memory Receive FIFO Allows the entire Ethernet frame to be received and wait in the FIFO while the receive byte count is analyzed The receive byte count is analyzed to determine the...

Page 164: ...DMA channel searches the four buffer descriptors starting with A and continuing with B C and D as necessary for an appropriately sized buffer The search stops when the DMA channel finds an available...

Page 165: ...ven low while the fifth nibble is being transferred The external CAM hardware monitors the MII receive interface between the PHY and the MAC waiting for the RPSF_ assertion When RPSF_ is asserted the...

Page 166: ...on Optional 100 Mbps physical coding sublayer PCS Optional 10 Mbps ENDEC interface Address filtering The 10 100 Mbps Ethernet MAC can be connected to the following devices through the MII 10 100 Mbps...

Page 167: ...andard 802 3x documentation for more information Host Host interface Provides a 16 bit interface for control and configuration CLKRST Clocks and resets Provides a central location for clock trees and...

Page 168: ...bits unless otherwise noted Note Reading or writing the MAC configuration registers address locations 0xFF80 0400 through 0xFF80 05DC is unreliable without valid clocks on the TXCLK and RXCLK input p...

Page 169: ...agement Write Data register FF80 0430 MRDD MII Management Read Data register FF80 0434 MIND MII Management Indicators register FF80 0438 SMII SMII Status register FF80 0440 SA1 Station Address Registe...

Page 170: ...MA mode provides higher performance out of the Ethernet chip and can be turned on and off Register bit assignment Note Bits D15 D00 are media control bits with D07 D00 used in ENDEC mode only ERX ETX...

Page 171: ...n 1520 bytes D28 R W ERXSHT 0 Accept short 60 bytes receive packets When set to 1 allows the MAC to accept packets that are smaller than 60 bytes The ERXSHT bit is used primarily for debugging D27 R W...

Page 172: ...FO full 11 Reserved Identifies the minimum number of bytes required in the transmit FIFO to initiate packet transmission A larger watermark setting increases transmit packet latency allowing for more...

Page 173: ...A Reads as zero D12 R W RXCINV 0 Invert the receive clock input Set to 1 only when the external Ethernet PHY generates a clock that is inverted in phase relative to what the MAC is expecting This bit...

Page 174: ...Station Address registers SA1 SA2 SA3 When ITXA is cleared the 7th through 12th bytes in the Ethernet packet are ignored and replaced by the size bytes in the MAC Address register D07 02 R W PDN AUI_T...

Page 175: ...l e MODE field Output based on EFE CSR bit Not b00 TXD1 PDN inverted open drain Not b00 TXD2 AUI_TP 1 Not b00 TXD3 AUI_TP 0 Not b00 TXER LNK_DIS_ Not b00 and not b11 MDC LPBK b11 MDC LPBK inverted No...

Page 176: ...MA interface logic DMA mode provides higher performance out of the Ethernet chip and can be turned on and off Register bit assignment RXFDB RXSKIP RXREGR TXREGE RXFIFOH TXFIFOH RXBR TXBC Bits Access M...

Page 177: ...se an interrupt when the ERFIFOH bit is set in the Ethernet General Control register D25 R C RXBR 0 Receive buffer ready Set to 1 when a new packet is available in the receive FIFO When set active hig...

Page 178: ...t General Control register D17 R C TXBC 0 Transmit buffer complete Set when packet transmission is complete When active high this bit can cause an interrupt when the EXTBC bit is also set in the Ether...

Page 179: ...st word of a transmit frame The first and middle words must use the primary address FF80 0008 Writing to the secondary address with the transmit interrupts disabled ETXBC in the Ethernet General Contr...

Page 180: ...ster Address FF80 0010 The Ethernet Transmit Status register contains the status for the last completed transmit buffer The transmit buffer complete bit TXBC is set in the Ethernet Bits Access Mnemoni...

Page 181: ...t is set to 1 the frame has been delivered and emptied from the transmit FIFO TXREGE and TXFIFOH in the Ethernet General Status register become active when the FIFO is ready to start receiving the nex...

Page 182: ...me making it impossible for the transmitter to try to transmit When this bit is set the transmit frame is automatically flushed from the transmit FIFO TXREGE and TXFIFOH in the Ethernet General Status...

Page 183: ...register become active when the FIFO is ready to start receiving the next packet TXBC in the Ethernet General Status register becomes active when TXAUR is set D08 R TXAJ 0 Transmit abort jumbo Set to...

Page 184: ...ts a precompiled CRC to be contained in the last four bytes of the Ethernet packet If the MAC finds that the precompiled CRC is incorrect the MAC sets the TXCRC bit in this Ethernet Transmit Status re...

Page 185: ...Provides the number of bytes contained in the next packet to be read from the Ethernet receive FIFO When using DMA mode the RXSIZE field is also copied to the buffer length field in the DMA buffer des...

Page 186: ...ng or DMA When the packet has been emptied RXREGR and RXFIFOH become inactive until the next receive buffer is ready D12 R RXBR 0 Receive broadcast packet Set to 1 to indicate that the next packet in...

Page 187: ...rame RXCV indicates that the PHY encountered invalid receive codes while receiving the data When this bit is set the RXREGR and RXFIFOH bits in the Ethernet General Status register remain inactive The...

Page 188: ...rate that information was received from the Ethernet medium for one of these reasons The DMA controller was not configured for bursting The memory peripheral device was not configured for bursting The...

Page 189: ...e MAC transmitter D13 12 N A Reserved N A N A D11 R W RPEMCSR 0 Reset PEMCS RX Set to 1 to reset the MAC control sublayer receive domain logic D10 R W RPERFUN 0 Reset PERFUN Set to 1 to reset the MAC...

Page 190: ...or all frames no matter the type normal or flow control 0 Deasserts PASS CURRENT RECEIVE FRAME for valid control frames D00 R W RXEN 0 Receive enable Set to 1 to allow the MAC receiver to receive fram...

Page 191: ...diately retransmits packets without backoff This reduces the chance of further collisions and ensures that transmit packets are sent D12 R W NOBO 0 No back off When this bit is set to 1 the MAC immedi...

Page 192: ...all short frames 0 Frames presented to the MAC have a valid length PADEN is used in conjunction with the Auto detect pad enable and VLAN pad enable fields See Table 62 PAD operation on page 181 for ad...

Page 193: ...heck is performed D00 R W FULLD 0 Full duplex 1 The MAC operates in full duplex mode 0 The MAC operates in half duplex mode It is recommended that you limit transmit frames to 512 bytes when full dupl...

Page 194: ...tted packet to the beginning of the next packet Full duplex mode The register value should be the proper period in nibble times minus 3 The recommended setting is h15 21d which represents these minimu...

Page 195: ...times out the MAC continues timing IPGR2 The transmitter causes a collision activating the random back off fairness algorithm ensuring fair access to the medium The range of values for IPGR1 is h0 IP...

Page 196: ...at transmission and includes the preamble and start frame delimiter SFD The default value for this field is h37 55d which corresponds to the frame byte count at the end of the window D07 04 N A Reser...

Page 197: ...thernet is 1518 octets A tagged frame adds four octets for a total of 1522 octets Program this field if you want a shorter maximum length restriction Note If a proprietary header is allowed adjust thi...

Page 198: ...rmal operation is enabled D05 R W NOCIPH 0 No cipher 1 enable The raw transmit 5B symbols are transmitted without ciphering 0 disable Normal ciphering occurs D04 R W DLINKF 0 Disable link fail 1 Disab...

Page 199: ...c within the PE10T in ENDEC mode D00 R W BITMODE 0 Bit mode Set this bit to 1 to configure the MAC to operate in ENDEC mode ENDEC mode is based on the bit clock rather than the nibble clock and change...

Page 200: ...se A transmit packet from the system is sent during backpressure D01 R W TPAUSE 0 Test pause Set this bit to 1 to allow the MAC Control sublayer to inhibit transmissions similar to receipt of a PAUSE...

Page 201: ...LKS field settings on page 190 for examples Note Some PHY devices support clock rates up to 12 5 MHz D01 R W SPRE 0 Suppress preamble 1 The MII management module performs read write cycles without the...

Page 202: ...a r e R e f e r e n c e R e v G 9 2 0 0 7 CLKS field SYS_CLK ratio 75 MHz example 12 MHz example 000 SYS_CLK 4 001 SYS_CLK 4 010 SYS_CLK 6 2 0 MHz 011 SYS_CLK 8 100 SYS_CLK 10 101 SYS_CLK 14 110 SYS_...

Page 203: ...ycles continuously This can be useful for monitoring link fail for example D00 R W READ 0 Single scan for read data When this bit is set to 1 the MII management module performs a single read cycle The...

Page 204: ...it PHY device address field for management cycles Up to 31 different PHY devices can be addressed address 0 is reserved D07 05 N A Reserved N A N A D04 00 R W RADR 0 MII PHY register address Represent...

Page 205: ...register is written an MII management write cycle is performed using the 16 bit data defined in the PHY Address register by the preconfigured PHY device and PHY register addresses The write operation...

Page 206: ...d data Provides read data following an MII management read cycle An MII management read cycle is executed by loading the PHY Address register then setting the READ bit in the MII Indicators register s...

Page 207: ...D01 R SCAN N A Automatically scan for read data in progress A 1 indicates that continuous MII management scanning read operations are in progress D00 R BUSY N A MII interface BUSY with read write ope...

Page 208: ...N A N A D04 R CLASH N A MAC to MAC with PHY A 1 indicates that MAC to MAC mode is selected but a PHY is detected D03 R JABBER N A Jabber condition present A 1 indicates that a Jabber condition is pres...

Page 209: ...dress octet 2 Holds the second octet of the station address bits 39 32 Table 77 Station Address Register 1 bit definition Bits Access Mnemonic Reset Description D31 16 N A Reserved N A N A D15 08 R W...

Page 210: ...ion D31 16 N A Reserved N A N A D15 08 R W OCTET5 h00 Station address octet 5 Holds the fifth octet of the station address bits 15 08 D07 00 R W OCTET6 h00 Station address octet 6 Holds the sixth octe...

Page 211: ...MAC to receive all multicast Ethernet packets without any filtering D01 R W PRA 0 Accept multicast packets using hash table 1 allows the MAC to receive only those multicast Ethernet packets that are...

Page 212: ...s each containing 16 bits The least significant bit of the first register corresponds to a CRC value of 0 The most significant bit of the last register corresponds to the CRC value of 63 The multicast...

Page 213: ...Mnemonic Reset Description D31 16 N A Reserved N A N A D15 00 R W HT2 0 CRC values 47 32 Table 83 HT3 bit definition Bits Access Mnemonic Reset Description D31 16 N A Reserved N A N A D15 00 R W HT4...

Page 214: ...id eth_load_mca_table void Description This routine loads the MCA table It generates a hash table for the MCA addresses currently registered and then loads this table into the NS7520 chip Parameters n...

Page 215: ...it hash table is then set Parameters hash_table pointer to buffer to store hash table in Return Values none static void eth_make_has_table WORD16 hash_table int index memset hash_table 0 8 clear hash...

Page 216: ...on int calculate_hash_bit BYTE mca Description This routine calculates which bit in the CRC hash table needs to be set for the NET 20UM to recognize incoming packets with the MCA passed to us Paramete...

Page 217: ...rd 0 mca_word 3 mca_word bp mcap mcap for bit_index 0 bit_index 16 bit_index bx WORD16 crc 16 get high word of crc bx rotate bx LEFT 1 bit 31 to lsb bx bp combine with incoming crc 1 shift crc left 1...

Page 218: ...E F E c o n f i g u r a t i o n 2 0 6 N S 7 5 2 0 H a r d w a r e R e f e r e n c e R e v G 9 2 0 0 7...

Page 219: ...r i a l C o n t r o l l e r M o d u l e Serial Controller Module C H A P T E R 1 0 The NS7520 supports two independent universal asynchronous synchronous receiver transmitter channels Each channel su...

Page 220: ...de 4 Mbps x16 mode 230 Kbits sec 32 byte TX FIFO 32 byte RX FIFO Programmable data format 5 to 8 data bits Odd even or no parity 1 2 stop bits Programmable channel modes Normal Local loopback Remote l...

Page 221: ...e Figure 24 shows the structure of the serial module Figure 24 Serial port block diagram Bit rate generator Each serial channel supports an independent programmable bit rate generator The bit rate gen...

Page 222: ...imple serial communications The UART receiver uses an over sampling technique to find the bit level framing of the UART protocol The framing protocol is as follows Start bit 0 Data 5 6 7 or 8 bits Par...

Page 223: ...tions on page 220 and Serial Channel registers on page 223 for information about signals and configuration SPI mode The SPI serial peripheral interface controller provides Full duplex synchronous inte...

Page 224: ...are memory mapped to the processor address space Transmit FIFO interface The processor can write either 1 2 or 4 bytes at a time to the transmit FIFO The number of bytes written is controlled by the...

Page 225: ...hannel registers and the DMA buffer descriptor block attached to DMA channels 8 and 10 To facilitate the use of transmit DMA the ETXDMA bit in Serial Channel Control Register A must be set active high...

Page 226: ...uffer closed status if desired b Write a 1 to the RBC bit position in Serial Channel Status Register A c Read Serial Channel Status Register A again 3 If RRDY is true a Read the data FIFO b Use the RX...

Page 227: ...73 and PORTC Configuration register on page 77 Configuration The SER module must be configured properly to operate in either master or slave mode For master mode operation the MODE field in Serial Ch...

Page 228: ...of the SPI clock signal while the SPI enable signal is driven active low The SPI slave devices should sample data in the rising edge of the SPI clock signal Drives the SPI enable signal active low fro...

Page 229: ...timer expires any residual RX data bytes are immediately written to the RX FIFO Note that some delay will occur in writing the final residual bytes the delay is determined by the configuration of the...

Page 230: ...ode 1 Reset the serial port by writing a 0 to Serial Channel Control Register a 2 Configure the Serial Channel Bit Rate register as shown EBIT 1 for enable TMODE 1 for 1x mode RXSRC 1 for external TXS...

Page 231: ...the rising edge of SPI clock until the SPI enable signal is driven inactive high While the SPI enable signal is inactive high the TXD output remains constant SPI slave receiver The SPI slave receiver...

Page 232: ...ose I O configurations The GEN module provides the physical layer connections for the NMSI Non Multiplexed Serial Interface and SPI interfaces NMSI is used for the UART protocol Use the appropriate GP...

Page 233: ...configuration space as shown Operating Mode Serial Port Maximum Rate UART x16 SYSCLK 64 UART x1 SYSCLK 4 SPI SYSCLK 6 Address Register FFD0 0000 Channel 1 Control Register A FFD0 0004 Channel 1 Contro...

Page 234: ...2 0 0 7 FFD0 004C Channel 2 Bit Rate register FFD0 0050 Channel 2 FIFO Data register FFD0 0054 Channel 2 Receive Buffer Gap Timer FFD0 0058 Channel 2 Receive Character Gap Timer FFD0 005C Channel 2 R...

Page 235: ...ort and the data FIFOs disables the serial channel 1 Enables serial channel operation The CE field cannot be set until the MODE field is configured in Serial Channel Control Register B D30 R W BRK 0 S...

Page 236: ...y enable When set parity is enabled for the UAT transmitter and receiver The transmitter generates proper parity The receiver checks for proper parity If the receiver encounters a bad parity bit the R...

Page 237: ...loopback Provides an internal local loopback feature When set to 1 the internal receive data stream is connected to the TXD output signal This field connects the serial channel receiver directly to th...

Page 238: ...t numbers and descriptions D08 R W ERXDMA 0 Enable receive DMA requests Enables the receiver to interact with a DMA channel When configured to operate in DMA mode the DMA controller empties the receiv...

Page 239: ...a DMA channel When configured to operate in DMA mode the DMA controller loads the transmit data FIFO from memory Clear this bit to pause the transmitter Bit Mnemonic Description D15 ERXBRT Receive br...

Page 240: ...G 9 2 0 0 7 Transmitter interrupts Bit Mnemonic Description D04 ERXCTS Change in CTS interrupt enable D03 ETXRDY Transmit register empty interrupt enable D02 ETXHALF Transmit FIFO half empty interrup...

Page 241: ...P timer Detects the maximum allowed time from when the first byte is placed into the receive data buffer and when the receive data buffer is closed When RBGT is set to 1 the BGAP field in Serial Chann...

Page 242: ...the Serial Shift register When BITORDR is set to 0 the bits are processed LSB first MSB last When BITORDR is set to 1 the bits are processed MSB first LSB last D18 16 N A Reserved N A N A D15 R W RTST...

Page 243: ...resented by a high level for the duration of the entire bit time a 0 is represented by a low level during the entire bit time NRZB 001 NRZB is NRZ inverted that is a 1 is represented by a low level du...

Page 244: ...t time Manchester 110 A 1 is represented by a high level during the first half of the bit time and a low level during the second half of the bit time A 0 is represented by a low level during the first...

Page 245: ...d in the DMA buffer descriptor when DMA operations are enabled and a buffer is closed The upper six bits of this register D31 26 can be cleared by writing a 1 to the respective bit position used when...

Page 246: ...ata match was found in the receive data stream and the current receive data buffer has been closed The last character in the receive data buffer contains the actual MATCH character When the receiver i...

Page 247: ...hen not using DMA BGAP is valid only while the RBC bit in this register is set D26 R CGAP 0 Character GAP timer Set when the enable receive character gap timer is set in Serial Channel Control Registe...

Page 248: ...s of the 4 byte long word contain valid data Normal Endian byte ordering rules apply to the Serial Channel FIFO Data register D19 R DCD 0 Current data carrier detect state 0 Inactive 1 Active Identifi...

Page 249: ...error interrupt pending Indicates that a receive parity error condition has been found Once set the RPE field remains set until acknowledged RPE is acknowledged by writing to this same bit position i...

Page 250: ...to generate an interrupt by setting the related IE bit in Serial Channel Control Register A RRDY is never active while RBC is active The RBC bit must be acknowledged to activate RRDY When the receive...

Page 251: ...bits are written automatically to the receive DMA buffer descriptor and the interlock between RBC and RRDY is handled automatically in the hardware D08 R RFULL 0 Receive FIFO full Indicates that the...

Page 252: ...gister A D03 R TRDY 0 Transmit register empty interrupt pending Indicates data can be written to the FIFO Data register TRDY typically is used only in interrupt driven applications it is not used for...

Page 253: ...d TBC is acknowledged by writing a 1 to this same bit position in this register The TBC bit is acknowledged automatically by hardware when the transmitter is configured to operate in DMA mode The TBC...

Page 254: ...RC or RXSRC set to 1 the serial channel is configured automatically to operate in 1X mode The serial channel clock is provided directly from the OUT1 OUT2 inputs through the PORTA PORTC interface Sett...

Page 255: ...26 R W TXEXT 0 Drive transmit clock external 0 Disable 1 Enable drive TXCLK out OUT2 signal at PORTC Enables the transmitter clock to be driven on the OUT2 signal attached to PORTC port When using the...

Page 256: ...clock Note When using SPI mode this bit must be set to zero D22 R W RXCINV 0 Receive clock invert 0 Normal RXD sampled on rising edge of RX clock 1 Inverted RXD sampled on falling edge of RX clock Con...

Page 257: ...ld match When DPLL is used in the application the selected TDCR RDCR value is a function of the transmitter encoding NRZ and NRZI modes can use the 1x configuration all other encoding must use 8x 16x...

Page 258: ...configuration provides the highest data rate 32x mode provides the highest resolution The TMODE bit in the Serial Channel Bit Rate register is maintained for NET ARM family backward compatibility Whe...

Page 259: ...receiver digital phase lock loop DPLL The BRG uses a divider mechanism for clock generation The DPLL extracts the clock from the incoming receive data stream D11 N A Reserved N A N A D10 00 R W NREG 0...

Page 260: ...1 230400 3686400 2 8 N 1 or 2 8 N 1 3686400 230400 or 2 8 N 1 16 or N 16 16 1 0 Max baudrate 8X 230 4K With the 18 432MHz crystal using SYSCLK as the clock source Max baudrate depends on speed grade M...

Page 261: ...1 152K These bit rate examples are generated by a bit rate generator using an 18 432 MHz quartz crystal N register Bit rate CLKMUX X1 mode X8 mode X16 mode 75 00 N A N A 1535 150 00 N A N A 767 300 00...

Page 262: ...ister empties the receive FIFO Data is available when the RRDY bit is set in Serial Channel Status Register A The RXFDB bits in Serial Channel Status Register A indicate how many bytes are available t...

Page 263: ...nel is configured to operate in interrupt mode the expiration of the timer causes an interrupt to be generated The receive buffer timer uses FXTALE and a 9 bit prescaler within the SER module The rece...

Page 264: ...er timer uses FXTALE and a 9 bit prescaler within the SER module The receive character timer is configured with a 10 bit programmable counter The effective buffer timer value is defined by this equati...

Page 265: ...he required value for the receive character timer is a function of the channel bit rate It is recommended that you set the character timer to a value that is 10 times the character period for the chan...

Page 266: ...masked using the Receive Match MASK register see Serial Channel 1 2 Receive Match MASK register on page 254 Register bit assignment Serial Channel 1 2 Receive Match MASK register Address FFD0 0020 60...

Page 267: ...24 R W RMMB1 0 Receive mask match byte 1 D23 16 R W RMMB2 0 Receive mask match byte 2 D15 08 R W RMMB3 0 Receive mask match byte 3 D07 00 R W RMMB4 0 Receive mask match byte 4 Table 95 Serial Channel...

Page 268: ...S e r i a l C h a n n e l r e g i s t e r s 2 5 6 N S 7 5 2 0 H a r d w a r e R e f e r e n c e R e v G 9 2 0 0 7...

Page 269: ...ctrical Characteristics C H A P T E R 1 1 This chapter provides the electrical specifications and timing relationships integral to NS7520 operation Electrical specifications include DC and AC characte...

Page 270: ...levels This table defines the DC operating thermal conditions for the NS7520 Operating the NS7520 outside these conditions results in unpredictable behavior Sym Parameter Conditions Min Typ Max Unit...

Page 271: ...ut detail tables and signal descriptions beginning on page 11 for information about which pins use pullup and pulldown resistors Sym Parameter Min Max Unit VIH Input high voltage 2 0 3 6 V VIL Input l...

Page 272: ...D C c h a r a c t e r i s t i c s 2 6 0 N S 7 5 2 0 H a r d w a r e R e f e r e n c e R e v G 9 2 0 0 7 Figure 28 Internal pullup characteristics Figure 29 Internal pulldown characteristics...

Page 273: ...s are based on the system configuration shown in Figure 30 with a 5pF allowance for PCB capacitance and a 0 25 ns allowance for PCB delay The timing of the buffers SDRAM and the like must be added to...

Page 274: ...s shown in Table 101 Signal Estimated load pF Device loads BCLK 23 Two SDRAMs 1 clock buffer clock input to PLD A 27 0 CAS 3 0 _ 23 Two SDRAM An 1 buffer PLD CS 4 0 _ 13 Two SDRAM CSn 1 buffer PLD DAT...

Page 275: ...stem dependent with an external oscillator It affects the setup and hold times of signals that change in the falling clock edges such as WE_ OE_ Recommendation Use a 3 3V 50 10 duty cycle oscillator w...

Page 276: ...N R1 OUT C2 10pF A 18 432MHz crystal or 55 296MHz oscillator allows full speed operation R4 0 OHM NC U1 LVC04 1 2 3 4 5 RESET_ K14 3R3V C3 100nF C1 10pF R2 0 OHM PLL bypassed U1 R2 OUT R1 IN R1 10K Y2...

Page 277: ...signals separately illustrate 0 to 1 and 1 to 0 transitions Inputs have setup hold times versus clock rising Outputs have switching time relative to either clock rising or clock falling Note Timing r...

Page 278: ...reset reset while power is at or above specified thresholds Before loss of valid power during power outage power down The PORTC4 output indicates the reset state of the chip PORTC4 persists beyond the...

Page 279: ...BCLK high to address valid 5 13 5 ns 9 BCLK high to data out valid 14 ns 13 BCLK high to data out high impedance 13 ns 10 Data in valid to BCLK high setup 5 ns 11 BCLK high to data in invalid hold 3 n...

Page 280: ...are required for DMA context switching 2 Port size determines which byte enable signals are active 8 bit port BE3 16 bit port BE 3 0 32 bit port BE 3 0 3 The TW cycles are present when the WAIT field...

Page 281: ...ock pulses are required for DMA context switching 2 Port size determines which byte enable signals are active 8 bit port BE3 16 bit port BE 3 0 32 bit port BE 3 0 3 The TW cycles are present when the...

Page 282: ...memory transfers can occur Thirteen clock pulses are required for DMA context switching 2 Port size determines which byte enable signals are active 8 bit port BE3 16 bit port BE 3 0 32 bit port BE 3...

Page 283: ...k pulses are required for DMA context switching 2 Port size determines which byte enable signals are active 8 bit port BE3 16 bit port BE 3 0 32 bit port BE 3 0 3 The TW cycles are present when the WA...

Page 284: ...en clock pulses are required for DMA context switching 2 Port size determines which byte enable signals are active 8 bit port BE3 16 bit port BE 3 0 32 bit port BE 3 0 3 The TW cycles are present when...

Page 285: ...n clock pulses are required for DMA context switching 2 Port size determines which byte enable signals are active 8 bit port BE3 16 bit port BE 3 0 32 bit port BE 3 0 3 The TW cycles are present when...

Page 286: ...ansfer is DMA Thirteen clock pulses are required for DMA context switching 2 Port size determines which byte enable signals are active 8 bit port BE3 16 bit port BE 3 0 32 bit port BE 3 0 3 The TW cyc...

Page 287: ...en clock pulses are required for DMA context switching 2 Port size determines which byte enable signals are active 8 bit port BE3 16 bit port BE 3 0 32 bit port BE 3 0 3 The TW cycles are present when...

Page 288: ...ransfer is DMA Thirteen clock pulses are required for DMA context switching 2 Port size determines which byte enable signals are active 8 bit port BE3 16 bit port BE 3 0 32 bit port BE 3 0 3 The TW cy...

Page 289: ...Unit 36 BCLK high to BE DQM valid 15 5 ns 6 BCLK high to non muxed address valid 5 13 5 ns 9 BCLK high to data out valid 14 ns 13 BCLK high to data out high impedance 13 ns 10 Data in valid to BCLK hi...

Page 290: ...ds depend on the address of the previous SDRAM access 3 If CAS latency 3 2 NOPs occur between the read and burst terminate commands 4 If CAS latency 3 3 inhibits occur after burst terminate 5 The TA a...

Page 291: ...n the address of the previous SDRAM access 3 If CAS latency 3 5 NOPs occur between the read and burst terminate commands 4 If CAS latency 3 3 inhibits occur after burst terminate 5 The TA and TEA LAST...

Page 292: ...recharge and or active commands are not always present These commands depend on the address of the previous SDRAM access 3 The TA and TEA LAST signals are for reference only T1 T2 T1 prechg active wri...

Page 293: ...nt These commands depend on the address of the previous SDRAM access When the active command is not present parameter 35 is valid during the write T2 cycle 3 The TA and TEA LAST signals are for refere...

Page 294: ...R e v G 9 2 0 0 7 SDRAM load mode SDRAM refresh prechg nop load 35 35 34 34 34 34 34 34 34 34 34 34 27 27 op code BCLK CS 4 0 CAS3 RAS CAS2 CAS CAS1 WE CAS0 A10 AP A 13 0 prechg inhibit refresh 34 34...

Page 295: ...ess valid 5 13 5 ns 9 BCLK high to data out valid 14 ns 13 BCLK high to data out high impedance 13 ns 10 Data in valid to BCLK high setup 5 ns 11 BCLK high to data in invalid hold 3 ns 14 TA valid to...

Page 296: ...rmines which byte enable signals are active 8 bit port BE3 16 bit port BE 3 2 32 bit port BE 3 0 3 Port size determines which CAS signals are active 8 bit port CAS3 16 bit port CAS 3 2 32 bit port CAS...

Page 297: ...e determines which byte enable signals are active 8 bit port BE3 16 bit port BE 3 2 32 bit port BE 3 0 3 Port size determines which CAS signals are active 8 bit port CAS3 16 bit port CAS 3 2 32 bit po...

Page 298: ...etermines which byte enable signals are active 8 bit port BE3 16 bit port BE 3 2 32 bit port BE 3 0 3 Port size determines which CAS signals are active 8 bit port CAS3 16 bit port CAS 3 2 32 bit port...

Page 299: ...e enable signals are active 8 bit port BE3 16 bit port BE 3 2 32 bit port BE 3 0 3 Port size determines which CAS signals are active 8 bit port CAS3 16 bit port CAS 3 2 32 bit port CAS 3 0 4 The TA an...

Page 300: ...p_refresh_cycles Fast page refresh RCYC 00 Fast page refresh RCYC 01 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RF8 T1 12 12 43 43 43 43 43 43 43 43 27 27 BCLK RAS 4 0 CAS3 CAS2 CAS1 CAS0 WE RF1 RF2 RF3 RF4 RF5 RF6...

Page 301: ...a c t e r i s t i c s Fast page refresh RCYC 10 Fast page refresh RCYC 11 RF1 RF2 RF3 RF4 RF5 RF8 T1 12 12 43 43 43 43 43 43 43 43 27 27 BCLK RAS 4 0 CAS3 CAS2 CAS1 CAS0 WE RF1 RF2 RF3 RF4 RF8 T1 12...

Page 302: ...Input drive CMOS buffer Num Description Min Max Unit 44 TXCLK high to TXD TXEN TXER valid 11 5 ns 45 RXD RXER RXDV TXCOL RXCRS valid to RXCLK high setup 3 ns 46 RXCLK high to RXD RXER RXDV TXCOL RXCRS...

Page 303: ...m 2 91 E l e c t r i c a l C h a r a c t e r i s t i c s Ethernet PHY timing Ethernet cam timing 49 48 47 46 45 44 TXCLK TXD 3 0 TXEN TXER RXCLK RXD 3 0 RXER RXDV CRS COL MDIO input MDC MDIO output 5...

Page 304: ...gram Temperature 15 00 min 110 00 max Voltage 1 60 min 1 40 max Output load 25 0pf Input drive CMOS buffer Num Description Min Max Units 54 TCK to TDO valid 21 ns 55 TCK to TDO HighZ 21 ns 56 TDI setu...

Page 305: ...rameters jtag bscan timing diagram Num Description Min Max Units 62 TCK to TDO valid 21 ns 63 TCK to TDO HighZ 21 ns 64 TDI setup to TCK rising 1 ns 65 TDI hold from TCK rising 3 ns 66 TRST width 1 TT...

Page 306: ...A timing parameters Temperature 15 00 min 110 00 max Voltage 1 60 min 1 40 max Output load 25 0pf Input drive CMOS buffer Num Description Min Max Unit 72 BCLK high to DACK valid 14 ns 75 BCLK high to...

Page 307: ...ddr 27 0 BE 3 0 CS RAS 4 0 CAS 3 0 RW OE WE and PORTC3 AMUX The timing of these signals depends on how the memory is configured Sync SRAM Async SRAM FP DRAM or SDRAM 2 The DONE signal works as an inpu...

Page 308: ...ometimes occurs between memory cycles 2 The memory signals are data 31 0 addr 27 0 BE 3 0 CS RAS 4 0 CAS 3 0 RW OE WE and PORTA2 AMUX The timing of these signals depends on how the memory is configure...

Page 309: ...external timing characteristics Temperature 15 00 min 110 00 max Voltage 1 60 min 1 40 max Output load 25 0pf Input drive CMOS buffer Num Description Min Max Unit 76 SCLK to ENABLE high 1 TSCLK 77 SC...

Page 310: ...m s 2 9 8 N S 7 5 2 0 H a r d w a r e R e f e r e n c e R e v G 9 2 0 0 7 synchronous serial internal clock synchronous serial external clock 79 78 77 77 76 76 SCLK Enable TXD RXD 84 83 82 82 81 81 80...

Page 311: ...ditions GPIO timing parameters GPIO timing diagram Temperature 15 00 min 110 00 max Voltage 1 60 min 1 40 max Output load 25 0pf Input drive CMOS buffer Num Description Min Max Unit 85 GPIO setup to B...

Page 312: ......

Page 313: ...3 01 NS7520 Errata C H A P T E R 1 2 This document contains information about NS7520 errata...

Page 314: ...0 0 7 How to identify the NS7520 There are three versions of the NS7520 each marked as shown in this sample The part number is constructed as follows product package rev id Commercial or Industrial s...

Page 315: ...transmitted instead of getting the next character from the transmit FIFO Software workarounds Modify these bits in Serial Channel Control register A Set the CTSTX bit bit 23 to 0 to disable hardware...

Page 316: ...e are intended to be shorter than the first cycle for faster transfers When a chip select is configured as EDO the wait states in the secondary cycles are incorrectly the sum of the WAIT and BCYC fiel...

Page 317: ...w w w d i g i e m b e d d e d c o m 3 05 N S 7 5 2 0 E r r a t a Workaround Use the Fast Page setting when using EDO DRAM...

Page 318: ...the configured frequency due to the internal PLL circuitry not being properly reset Note When the PLL is bypassed PLLTST_N BISTEN_N and SCANEN_N all equal a logic 1 and this erratum does not apply Wor...

Page 319: ...SET_N source with a rise time exceeding 18ns 0 8V to 2 0V should use a Schmitt trigger speedup circuit such as 74LVC2G14 NC U4 74LVC1G04 1 2 3 4 5 NS7520 A10 U3 MAX811S 1 2 4 3 GND RST V MR 3 3V L13 S...

Page 320: ...xhibits no operational failures Workaround 1 For existing designs Cut the pin R13 P12 and N12 traces to the VCC supply connection This will float pins R13 P12 and N12 It is advisable to modify the PCB...

Page 321: ...an 128 MB is written in the Chip Select Option register mask word In particular if the SDRAM is located at 0 256M and one read is done at address 0x400 and another read is done at address 0x0 there is...

Page 322: ...oes not filter multicast and broadcast packets in a predictable manner Workaround Program the Station Address Filter register SAFR fields as shown If filtering of multicast and broadcast packets is re...

Page 323: ...then dropped For those Ethernet packets where the higher level protocol does not provide a checksum corrupted data might be passed to the application The problem frequency has been measured at Digi Te...

Page 324: ...Status Register A When the bit indicates empty allow 1 character time to let the last character exit the shift register 3 Using TXHALF interrupt You can use this method when filling the FIFO using wor...

Page 325: ...d not have a problem with this issue when working in DMA mode External use of TA_ and TEA_ Note these issues for TA_ and TEA_ TEA_ Externally generated TEA_ burst cycles can cause failures TA_ Externa...

Page 326: ...N S 7 5 2 0 e r r a t a 3 1 4 N S 7 5 2 0 H a r d w a r e R e f e r e n c e R e v G 9 2 0 0 7...

Page 327: ...w w w d i g i e m b e d d e d c o m 3 15 N S 7 5 2 0 E r r a t a...

Page 328: ......

Page 329: ...ield 181 B Back to Back Inter Packet Gap register 182 BASE field 88 93 baudrates with different clock sources 247 BBus arbitration 44 BBus master and slave modules 44 BBus module 43 45 address decodin...

Page 330: ...nput 259 outputs 259 recommended operating conditions 258 demand paged virtual memory system 36 DMA buffer descriptor 131 133 DMA channel assignments 133 DMA Control register 137 DMA controller 2 128...

Page 331: ...156 EFE module 150 153 features 150 high level structure 150 receive buffer descriptor selection 152 receive FIFO 151 receive processing 151 transmit FIFO 151 transmit processing 151 Ethernet General...

Page 332: ...external peripheral DMA support 146 148 external reset circuit source 59 F fast interrupt request exception See FIRQ exception FIFO management receive FIFO interface 213 SPI 212 transmit FIFO interfac...

Page 333: ...nable Set 81 Interrupt Status Enabled 81 Interrupt Status Raw 81 interrupt enable bits 143 Interrupt Enable Clear register 81 Interrupt Enable register 81 Interrupt Enable Set register 81 interrupt pe...

Page 334: ...t unit MMU 36 Memory Module Configuration register 89 memory space 89 memory timing control fields 97 101 memory to memory mode DMA buffer descriptor 131 external transfers 147 memory to memory operat...

Page 335: ...upts 80 outputs 79 PORTC0 80 PORTC4 80 readback 80 PORTC Configuration register 77 PORTC interrupts 41 power 3 power supply 28 prefetch abort exception 32 35 processor interrupts vs DMA 213 programmab...

Page 336: ...9 Serial Channel 1 2 FIFO registers 250 Serial Channel 1 2 Receive Buffer Gap Timer 250 Serial Channel 1 2 Receive Character Gap Timer 252 Serial Channel 1 2 Receive Match MASK register 254 Serial Cha...

Page 337: ...register 63 system mode test support pinout 25 System Status register 68 T test modes 48 Test register 187 Thumb architecture 30 timeout interval equations 70 timer 1 interrupts 40 timer 2 interrupts...

Page 338: ...1 0 N S 7 5 2 0 H a r d w a r e R e f e r e n c e R e v G 9 2 0 0 7...

Page 339: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Digi International NS7520B 1 C55 NS7520B 1 I55...

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