E F E c o n f i g u r a t i o n
1 8 6
N S 7 5 2 0 H a r d w a r e R e f e r e n c e , R e v G 9 / 2 0 0 7
PHY Support register
Address: FF80 0418
Register bit assignment
Bits
Access
Mnemonic
Reset
Description
D31:08
N/A
Reserved
N/A
N/A
D07
R/W
RPE100X
0
Reset PE100X module
Set this bit to 1 to reset the PE100X module, which contains
the 4B/5B symbol encipher/decipher logic.
Must be set if not using 4B/5B logic.
D06
R/W
FORCEQ
0
Force quiet
1
Transmit data is quieted, which allows the cipher
contents to be output.
0
(clear) Normal operation is enabled.
D05
R/W
NOCIPH
0
No cipher
1
(enable) The raw transmit 5B symbols are transmitted
without ciphering.
0
(disable) Normal ciphering occurs.
D04
R/W
DLINKF
0
Disable link fail
1
Disables the 330 ms link fail timer, allowing for
shorter simulations.
0
(clear) Normal operation occurs.
D03
R/W
RPE10T
0
Reset PE10T module
Set this bit to 1 to reset the PE10T module. This module
converts the MII nibble-streams to the serial bit stream for
ENDEC transceivers.
Must be set if not using the PE10T module.
Table 67: PHY Support register bit assignment
13
12
11
10
9
8
7
6
5
4
3
2
1
0
15
14
31
29
28
27
26
25
24
23
22
21
20
19
18
17
16
30
Reserved
Reserved
RPE
100X
FORCEQ
NO
CIPH
DLINK
F
RPE
10T
Rsvd
JAB-
BER
BIT
MODE
Summary of Contents for NS7520B Series
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Page 313: ...3 01 NS7520 Errata C H A P T E R 1 2 This document contains information about NS7520 errata...
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