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3
BIOS Setup
DRAM Frequency
Selects the operating frequency of the DRAM.
Configure DRAM Timing by SPD
The EEPROM on a DIMM has SPD (Serial Presence Detect) data
structure that stores information about the module such as the
memory type, memory size, memory speed, etc. When this field is
enabled, the system will run according to the information in the
EEPROM.
Disabled
Enabled
BIOS SETUP UTILITY
v02.61 (C)Copyright 1985-2006, American Megatrends, Inc.
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North Bridge Chipset Configuration
DRAM Frequency
[Auto]
Configure DRAM Timing by SPD
[Enabled]
DRAM CAS# Latency
[5]
DRAM RAS# to CAS# Delay [5 DRAM Clocks]
DRAM RAS# Precharge [5 DRAM Clocks]
DRAM RAS# Activate to Precha [15 DRAM Clocks]
Boots Graphic Adapter Priority
[PCI/IGD]
Internal Graphics Mode Select
[Enabled, 8MB]
X
Video Function Configuration
Chipset
Options
DRAM CAS# Latency
This field is used to select the clock cycle of the SDRAM CAS
latency time. The option selected specifies the time before SDRAM
starts a read command after receiving it.
DRAM RAS# to CAS# Delay
This field is used to select the latency between the DRAM active
command and the read/write command.
DRAM RAS# Precharge
This field is used to select the idle clock after issuing a precharge
command to the DRAM.
