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BIOS Setup
Read Preamble Value
When the DQS receiver is turned on, you can select the time prior
to the max-read DQS return. This will notify the controller on when
to enable its DQS receiver when awaiting the DRAM DQS driver
to turn on for a read. The controller will disable its DQS receiver
until the read preamble time and then enable its DQS receiver while
the DRAM asserts DQS.
Async Latency Value
This field is used to select a value equal to the maximum asynchro-
nous latency in the DRAM read round-trip loop.
DRAM Bank Interleaving
The options are Enabled and Disabled.
Burst Length
This field is used to select the DRAM’s burst length. The DRAM will
predict the address of the next memory location to be accessed
after the first address is accessed. To use the burst feature, select the
burst length which is the actual length of burst plus the starting
address and allows internal address counter to properly generate
the next memory location. The larger the size, the faster the DRAM
performance.
Enable All DIMM Clock
This field is used to enable or disable all DIMM clock.
MTRR Mapping Mode
This field is used to disable or continue the MTRR mapping mode.