Page 2
Indeterminate Power-On State
On power-on, the run/stop flip-flop on the front panel board is not initialized and the 8080
processor is not given a reset signal. These omissions tend to leave the 8080 in an invalid
state on power-on. This is why the “STOP/RESET” switch sequence is required to put the
computer into a valid state. This fix can be optionally enabled or left like the original.
Reset not Synchronized with phi2
An undocumented 8080 reset timing requirement is that reset be released a minimum of
about 200ns prior to the rising edge of phi2. This is implemented in the Intel 8224 clock gen-
erator that was used on the 8800b CPU board, but this chip is not used on the original Altair
CPU board. The new front panel board enforces this timing for resets generated by the front
panel.
Front Panel PRDY Output is not Open Collector
Clients on the bus should drive the PRDY signal with an open collector driver. The signal is
terminated on the CPU board with a 1K pull-up resistor. However, the original front panel
board actively drives this signal high. Therefore, when any bus client drives PRDY low to in-
sert wait states, its output driver is sinking the active high drive of the front panel’s PRDY
driver.
6) Enhancements
In addition to duplicating the functionality of the original front panel board, the 8800c front panel
board set offers several enhancements that can be optionally enabled:
• An output latch at I/O address 0FFh that can display on the data LEDs (similar to IMSAI 8080)
• Auto repeat single-step at selectable rate from 1hz-8hz, similar to the 8800b
• Code snippet injection: Common Altair bootstrap loaders, port echo routines, Kill-the-Bit, etc.
can be injected into RAM by selecting the desired code snippet on the lower eight address
switches, then depressing the AUX-Left switch.
• Auto jump on power-on (can be independent of reset operation)
• Auto jump on reset (can be independent of power-on operation)
