Denon DRA-100, Service Manual

Page: 71 / 98

Pin Name Function Description
69 GPIO_5 Bidirectional, pull-down GPIO
70 TEST Input, pull-down Test mode, tie to ground
71 SPI_CK Input, pull-down SPI control input clock
72 SPI_CS Input, pull-down SPI control input chip select
73 SPI_DATA Bidirectional, pull-down SPI control data input/output
74 P1V8 - 1.8 V core supply
75 GND - Ground
76 P3V3 - 3.3 V I/O supply
77 GPIO_6 Bidirectional, pull-down GPIO
78 GPIO_7 Bidirectional, pull-down GPIO
79 VPD - Test mode, tie to ground
80 CH_4_5_AUDIO_WS Input, pull-down Channels 4, 5 audio input word clock
81 CH_4_5_AUDIO_SD Input, pull-down Channels 4, 5 audio input data
82 CH_4_5_AUDIO_SCK Input, pull-down Channels 4, 5 audio input bit clock
83 CH_6_7_AUDIO_WS Input, pull-down Channels 6, 7 audio input word clock
84 CH_6_7_AUDIO_SD Input, pull-down Channels 6, 7 audio input data
85 CH_6_7_AUDIO_SCK Input, pull-down Channels 6, 7 audio input bit clock
86 P1V8 - 1.8 V core supply
87 GND - Ground
88 P3V3 - 3.3 V I/O supply
89 CH7_PWM0 Output Channel 7 low side drive
90 CH7_PWM1 Bidirectional, pull-down Channel 7 high side drive or channel 6/7
PWM sense control
91 CH7_PWM2 Output Channel 7 high side drive
92 CH6_PWM0 Output Channel 6 low side drive
Production Information
© 2012 Cambridge Silicon Radio Limited
This material is subject to CSR's non-disclosure agreement.
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Direct Digital Feedback
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Data Sheet
Pin Name Function Description
93 CH6_PWM1 Bidirectional, pull-down Channel 6 high side drive or channel 6/7
PWM sense control
94 CH6_PWM2 Output Channel 6 high side drive
95 P3V3 - 3.3 V I/O supply
96 GND - Ground
97 CH5_PWM0 Output Channel 5 low side drive
98 CH5_PWM1 Bidirectional, pull-down Channel 5 high side drive or channel 4/5
PWM sense control
99 CH5_PWM2 Output Channel 5 high side drive
100 CH4_PWM0 Output Channel 4 low side drive
101 CH4_PWM1 Bidirectional, pull-down Channel 4 high side drive or channel 4/5
PWM sense control
102 CH4_PWM2 Output Channel 4 high side drive
103 P3V3 - 3.3 V I/O supply
104 GND - Ground
105 P1V8 - 1.8 V core supply
106 C7P1V8 - 1.8 V core supply (quiet)
107 CH7_REF0 Output, tristate Channel 7 reference 0 output
108 C7P3V3 - 3.3 V I/O supply (quiet)
109 C7GND - Ground
110 CH7_REF1 Output, tristate Channel 7 reference 1 output
111 CH7_REF2 Output, tristate Channel 7 reference 2 output
112 CH7_FB0 Bidirectional, pull-up Channel 7 low resolution feedback input
or channel 6/7 I²S output word clock
113 CH7_FB1 Bidirectional, pull-up Channel 7 high resolution feedback input
or channel 6/7 I²S output data
114 C67P1V8 - 1.8 V core supply (quiet)
Production Information
© 2012 Cambridge Silicon Radio Limited
This material is subject to CSR's non-disclosure agreement.
Page 19 of 181
CS-225959-DSP6
www.csr.com
CSRA6600
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CSRA
6601
Direct Digital Feedback
A
m
plifier
Data Sheet
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