Denon DRA-100, Service Manual

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MX25L25635FMI (IC1304)
MX25L25635FMI Pin Discriptions
MX25L25635FMI Block Diagram
7
REV. 1.2, AUG. 09, 2013 P/N: PM1738
3. PIN CONFIGURATIONS
4. PIN DESCRIPTION
SYMBOL DESCRIPTION
Chip Select
SI/SIO0
Serial Data Input (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
SO/SIO1
Serial Data Output (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
SCLK Clock Input
Write protection: connect to GND or
Serial Data Input & Output (for 4xI/O
read mode)
Hardware Reset Pin Active low or
Serial Data Input & Output (for 4xI/O
read mode)
DNU/SIO3 Do not use or Serial Data Input &
Output (for 4xI/O read mode)
Hardware Reset Pin Active low
GND Ground
NC No Connection
16-PIN SOP (300mil)
1
2
3
4
5
6
7
8
DNU/SIO3
VCC
RESET#
NC
NC
NC
CS#
SO/SIO1
16
15
14
13
12
11
10
9
SCLK
SI/SIO0
NC
NC
NC
NC
GND
WP#/SIO2
8-WSON (8x6mm)
Notes:
2. When using 1I/O or 2I/O (QE bit not enable), the
DNU/SIO3 pin of 16SOP can not connect to GND.
7
REV. 1.2, AUG. 09, 2013 P/N: PM1738
3. PIN CONFIGURATIONS
4. PIN DESCRIPTION
SYMBOL DESCRIPTION
Chip Select
SI/SIO0
Serial Data Input (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
SO/SIO1
Serial Data Output (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
SCLK Clock Input
Write protection: connect to GND or
Serial Data Input & Output (for 4xI/O
read mode)
Hardware Reset Pin Active low or
Serial Data Input & Output (for 4xI/O
read mode)
DNU/SIO3 Do not use or Serial Data Input &
Output (for 4xI/O read mode)
Hardware Reset Pin Active low
GND Ground
NC No Connection
16-PIN SOP (300mil)
1
2
3
4
5
6
7
8 DNU/SIO3
VCC
RESET#
NC
NC
NC
CS#
SO/SIO1
16
15
14
13
12
11
10
9
SCLK
SI/SIO0
NC
NC
NC
NC
GND
WP#/SIO2
8-WSON (8x6mm)
Notes:
2. When using 1I/O or 2I/O (QE bit not enable), the
DNU/SIO3 pin of 16SOP can not connect to GND.
8
REV. 1.2, AUG. 09, 2013 P/N: PM1738
5. BLOCK DIAGRAM
74