13
DHT-500SD
HY57V651620BTC-75 (ME: U11)
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
BA0,BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
Multiplexed data input / output pin
Power supply for internal circuits and input buffers
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
V
SS
DQ15
V
SSQ
DQ14
DQ13
V
DDQ
DQ12
DQ 11
V
SSQ
DQ10
DQ 9
V
DDQ
DQ 8
V
SS
NC
UD QM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DD
DQ 0
V
DDQ
DQ 1
DQ 2
V
SSQ
DQ 3
DQ 4
V
DDQ
DQ 5
DQ 6
V
SSQ
DQ 7
V
DD
LDQM
/W E
/CAS
/RAS
/CS
BA0
BA1
A10/A P
A0
A1
A2
A3
V
DD
PIN DESCRIPTION
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