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PIN DESCRIPTION
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FUNCTION DESCRIPTION
Port 3.7 GPIO
8051 P3.7 GPIO.
SPICLK
It behaves as the Master clock output (Master Mode), or Slave clock input (Slave
Mode) of the on-chip SPI interface.
PGAVMID
P3.7
I/O, A
1
PGA VMID output.
Port 3.6 GPIO
8051 P3.6 GPIO.
MISO
It behaves Master data Input of the on-chip SPI interface (Master Mode), or Slave data
Output of the SPI interface (Slave Mode).
PGAIN2
P3.6
I/O, A
2
PGA IN2.
Port 3.5 GPIO
8051 P3.5 GPIO.
MOSI
It behaves Master data Output of the on-chip SPI interface (Master Mode), or Slave
data Input of the SPI interface (Slave Mode).
PGAOUT2
P3.5
I/O, A
3
PGA OUT2.
Port 2.3 GPIO
8051 P2.3 GPIO.
RXD1
P2.3
I/O
4
This pin also can be configured as RXD of UART 1.
Port 2.2 GPIO
8051 P2.2 GPIO.
TXD1
P2.2
I/O
5
This pin also can be configured as TXD of UART 1.
Port 2.1 GPIO
8051 P2.1 GPIO. To allow proper operation as GPIO P2.1 function, crystal oscillator
must be disabled by setting XOSCCFG register to 0x00.
XOUT Crystal Oscillator Output
P2.1
I/O, A
6
This pin also can be configured as XOUT for crystal oscillator. XOUT is in parallel
connection with the GPIO pin. To enable this pin as XOUT, the IOCFGP2.1 must be
cleared to 0x00.
Port 2.0 GPIO
8051 P2.0 GPIO. To allow proper operation as GPIO P2.0 function, crystal oscillator
must be disabled by setting XOSCCFG register to 0x00.
XIN Crystal Oscillator Input
P2.0
I/O, A
7
This pin also can be configured as XIN for crystal oscillator. XIN is in parallel
connection with the GPIO pin. To enable this pin as XIN, the IOCFGP2.0 must be
cleared to 0x00.
