Denon AVR-S940H, Service Manual

Page: 56 / 173

AD8195ACPZ (F_HDMI : U3000)
Terminl Function
Block diagram
NOTES
1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF
THE PACKAGE THAT AIDS IN HEAT DISSIPATION. THE PAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER
TO MEET THERMAL SPECIFICATIONS.
AD8195
TOP VIEW
(Not to Scale)
1 IN0
2 IP0
3 IN1
4 IP1
5 VTTI
6 IN2
7 IP2
10 AVCC
30 AVCC
29 PE_EN
28 TX_EN
27 AVEE
26 AVCC
25 AVCC
24 AVEE
21 COMP
40
SC
L_
IN
39
SDA_
IN
38
C
EC_
IN
37
A
VE
E
36
VR
EF
_I
N
35
SC
L_
O
U
T
34
SDA_
O
U
T
31
C
EC_
O
U
T
11
O
N
0
12
O
P0
13
VT
TO
14
O
N
1
15
O
P1
16
A
VC
C
17
O
N
2
20
O
P3
9 IP3
8 IN3
22 AVCC
23 AVCC
19
O
N
3
18
O
P2
32
A
M
U
XV
C
C
33
VR
EF
_O
U
T
PIN 1
INDICATOR
07
04
9-
00
3
AD8195
Rev. 0 | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. THE AD8195 LFCSP HAS AN EXPOSED PAD ON THE UNDERSIDE OF
THE PACKAGE THAT AIDS IN HEAT DISSIPATION. THE PAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER
TO MEET THERMAL SPECIFICATIONS.
AD8195
TOP VIEW
(Not to Scale)
1 IN0
2 IP0
3 IN1
4 IP1
5 VTTI
6 IN2
7 IP2
10 AVCC
30 AVCC
29 PE_EN
28 TX_EN
27 AVEE
26 AVCC
25 AVCC
24 AVEE
21 COMP
40
SC
L_
IN
39
SDA_I
N
38
CE
C_I
N
37
A
VEE
36
VR
EF
_I
N
35
SCL
_O
UT
34
SDA_O
U
T
31
CE
C_O
U
T
11
O
N0
12
O
P0
13
VT
TO
14
O
N1
15
O
P1
16
AV
CC
17
O
N2
20
O
P3
9 IP3
8 IN3
22 AVCC
23 AVCC
19
O
N3
18
O
P2
32
AM
U
XV
CC
33
VR
EF
_O
U
T
PIN 1
INDICATOR
07
04
9-
00
3
Figure 3. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type 1 Description
1 IN0 HS I High Speed Input Complement.
2 IP0 HS I High Speed Input.
3 IN1 HS I High Speed Input Complement.
4 IP1 HS I High Speed Input.
5 VTTI Power Input Termination Supply. Nominally connected to AVCC.
6 IN2 HS I High Speed Input Complement.
7 IP2 HS I High Speed Input.
8 IN3 HS I High Speed Input Complement.
9 IP3 HS I High Speed Input.
10, 16, 22, 23, 25, 26, 30 AVCC Power Positive Analog Supply. 3.3 V nominal.
11 ON0 HS O High Speed Output Complement.
12 OP0 HS O High Speed Output.
13 VTTO Power Output Termination Supply. Nominally connected to AVCC.
14 ON1 HS O High Speed Output Complement.
15 OP1 HS O High Speed Output.
17 ON2 HS O High Speed Output Complement.
18 OP2 HS O High Speed Output.
19 ON3 HS O High Speed Output Complement.
20 OP3 HS O High Speed Output.
21 COMP Control Power-On Compensation Pin. Bypass to ground through a 10 μF capacitor.
24, 27, 37, Exposed Pad AVEE Power Negative Analog Supply. 0 V nominal.
28 TX_EN Control High Speed Output Enable Parallel Interface.
29 PE_EN Control High Speed Preemphasis Enable Parallel Interface.
31 CEC_OUT LS I/O CEC Output Side.
32 AMUXVCC Power Positive Auxiliary Buffer Supply. 5 V nominal.
IP[3:0]
IN[3:0]
VTTI
OP[3:0]
AMUXVCC
AVEE
VTTO
AVCC
ON[3:0]
VREF_IN VREF_OUT
+
– +
–
EQ
BUFFER
PE
CONTROL
LOGIC
4
4 4
2 2
4
HIGH SPEED BUFFERED
LOW SPEED BUFFERED
PE
_E
N
TX
_E
N
C
O
M
P
PARALLEL
BIDIRECTIONAL
AD8195
SCL_IN
SDA_IN
SCL_OUT
SDA_OUT
CEC_IN CEC_OUT
PCM9211 (DIGITAL : U1040)
PIN Functions
PIN
DESCRIPTION
NO. NAME I/O
5-V
TOLERANT
1 ERROR/INT0 O No DIR Error detection output / Interrupt0 output
2 NPCM/INT1 O No DIR Non-PCM detection output / Interrupt1 output
3 MPIO_A0 I/O Yes Multipurpose I/O, Group A(1)
4 MPIO_A1 I/O Yes Multipurpose I/O, Group A(1)
5 MPIO_A2 I/O Yes Multipurpose I/O, Group A(1)
6 MPIO_A3 I/O Yes Multipurpose I/O, Group A(1)
7 MPIO_C0 I/O Yes Multipurpose I/O, Group C(1)
8 MPIO_C1 I/O Yes Multipurpose I/O, Group C(1)
9 MPIO_C2 I/O Yes Multipurpose I/O, Group C(1)
10 MPIO_C3 I/O Yes Multipurpose I/O, Group C(1)
11 MPIO_B0 I/O Yes Multipurpose I/O, Group B(1)
12 MPIO_B1 I/O Yes Multipurpose I/O, Group B(1)
13 MPIO_B2 I/O Yes Multipurpose I/O, Group B(1)
14 MPIO_B3 I/O Yes Multipurpose I/O, Group B(1)
15 MPO0 O No Multipurpose output 0
16 MPO1 O No Multipurpose output 1
17 DOUT O No Main output port, serial digital audio data output
18 LRCK O No Main output port, LR clock output
19 BCK O No Main output port, Bit clock output
20 SCKO O No Main output port, System clock output
21 DGND – – Ground, for digital
22 DVDD – – Power supply, 3.3 V (typ.), for digital
23 MDO/ADR0 I/O Yes Software control I/F, SPI data output / I2C slave address
setting0(2)
24 MDI/SDA I/O Yes Software control I/F, SPI data input / I2C data input/output(2)
(3)
25 MC/SCL I Yes Software control I/F, SPI clock input / I2C clock input(2)
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
ERROR/INT0
NPCM/INT1
MPIO_A0
MPIO_A1
MPIO_A2
MPIO_A3
MPIO_C0
MPIO_C1
MPIO_C2
MPIO_C3
MPIO_B0
MPIO_B1
VDDRX
RXIN1
RST
RXIN2
RXIN3
RXIN4/ASCKIO
RXIN5/ABCKIO
RXIN6/ALRCKIO
RXIN7/ADIN0
MODE
MS/ADR1
MC/SCL
48 47 46 45 44 43 42 41 40 39 38
13 14 15 16 17 18 19 20 21 22 23
37
24
PCM9211
VINR VINL VCCAD AGNDAD VCOM FIL
T
VCC AGND XTO XTI GNDRX RXIN0
MPIO_B2 MPIO_B3
MPO0 MPO1 DOUT
LRCK
BCK
SCK
O
DGND DVDD
MDO/ADR0
MDI/SDA
PCM9211
www.ti.com SBAS495 –JUNE 2010
PIN CONFIGURATIONS
PT PACKAGE
LQFP-48
(TOP VIEW)
PIN FUNCTIONS
PIN
5-V
NO. NAME I/O TOLERANT DESCRIPTION
1 ERROR/INT0 O No DIR Error detection output / Interrupt0 output
2 NPCM/INT1 O No DIR Non-PCM detection output / Interrupt1 output
3 MPIO_A0 I/O Yes Multipurpose I/O, Group A (1)
4 MPIO_A1 I/O Yes Multipurpose I/O, Group A
(1)
5 MPIO_A2 I/O Yes Multipurpose I/O, Group A (1)
6 MPIO_A3 I/O Yes Multipurpose I/O, Group A
(1)
7 MPIO_C0 I/O Yes Multipurpose I/O, Group C (1)
8 MPIO_C1 I/O Yes Multipurpose I/O, Group C
(1)
9 MPIO_C2 I/O Yes Multipurpose I/O, Group C (1)
10 MPIO_C3 I/O Yes Multipurpose I/O, Group C
(1)
11 MPIO_B0 I/O Yes Multipurpose I/O, Group B (1)
12 MPIO_B1 I/O Yes Multipurpose I/O, Group B
(1)
13 MPIO_B2 I/O Yes Multipurpose I/O, Group B (1)
14 MPIO_B3 I/O Yes Multipurpose I/O, Group B
(1)
15 MPO0 O No Multipurpose output 0
(1) Schmitt trigger input
Copyright © 2010, Texas Instruments Incorporated
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Product Folder Link(s): PCM9211
Before Servicing
This Unit
Electrical
Mechanical
Repair Information
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