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W9864G6JH-6 Block diagram
W9864G2IH
Publication Release Date: Aug. 28, 2009
- 6 -
Revision A03
6. BLOCK DIAGRAM
DQ0
DQ31
DQM0~3
CLK
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #2
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #3
DATA CONTROL
CIRCUIT
DQ
BUFFER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
NOTE:
The cell array configuration is 2048 * 256 * 32
ROW
DE
CODE
R
ROW
DE
CODE
R
ROW
DE
CODE
R
ROW
DE
CODE
R
A0
A9
BS0
BS1
CS
RAS
CAS
WE
Summary of Contents for AVR-1712
Page 22: ...22 Personal notes ...
Page 66: ...66 Personal notes ...
Page 131: ...131 AK5358BET HDMI IC30 AK5358BET Pin Function ...
Page 141: ...141 TC4052BFT AV IC806 826 TC4051BFT AV IC822 NJM2586AM AV IC825 ...
Page 142: ...142 2 FL DISPLAY FLD 18 ST 13GINK FRONT U100 PIN CONNECTION GRID ASSIGNMENT ...
Page 143: ...143 ANODE CONNECTION ...