A x e l H a r d w a r e M a n u a l
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7.4.4
MIPI DSI
AXEL provides the MIPI Display interface derived from the
i.MX6 integrated MIPI-DSI host controller, which acts as a
bridge between the IPU and the MIPI D-PHY, enabling the
communication with a MIPI-DSI compliant display through up
to two D-PHY Data Lanes.
The following table describes the interface signals:
Pin name
Conn.
Pin
Function
Notes
DSI_CLK0M
J3.34
MIPI Display
Differential clock pair
DSI_CLK0P
J3.36
DSI_D0M
J3.40
MIPI Display
Differential data 0
pair
DSI_D0P
J3.42
DSI_D1M
J3.46
MIPI Display
Differential data 1
pair
DSI_D1P
J3.458
7.5
Video Input ports
This section will be completed in a future version of this
manual.
7.5.1
Parallel RGB
This section will be completed in a future version of this
manual.
7.5.2
MIPI CSI
This section will be completed in a future version of this
manual.
7.6
UARTs
Five UART ports are routed to AXEL connectors. UART1
provides full Modem Control Signals, while UART2, UART3,
UART4 and UART5 are 4-wire interfaces. Each port can be
programmed separately (also in IrDA mode).
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