A x e l H a r d w a r e M a n u a l
v . 1 . 0 . 4
can be drawn.
●
PMIC_VSNVS: PMIC's LDO or coin cell output to
processor. Please refer to PMIC's datasheet for current
limit. Please take into account internal loads as depicted
in AXEL reset scheme picture.
●
PMIC_SWBST_SUPPLY: this rail is connected to PMIC's
SWBSTIN pad and can be used to power SWBST boost
regulator. This regulator is not used by any AXEL's
internal load. Output voltage can be selected by user.
●
PMIC_5V: this is output of SWBST boost regulator. This
regulator is not used by any AXEL's internal load. Output
voltage can be selected by user.
●
VDDCORE, VDDSOC, DDR_1V5, 1V2_ETH,
VDDHIGH_VPH, VDDSOC_CAP, VDDPU,
VDD_ARM23_CAP, VDD_ARM01_CAP, VDGEN5_2V8,
VDD_BUS_CAP, VDD_SNVS_CAP, VGEN3_2V5,
NVCC_PLL_OUT: these signals route power voltage
generated by AXEL PSU. These optional signals (in the
default configuration, the pins are dedicated to other
functions ) are meant to enable monitoring of internal
voltages by carrier board circuitry. For further details,
please refer to pinout table.
For further details, please refer to the PMIC documentation:
http://www.freescale.com/webapp/sps/site/prod_summary.jsp?
code=MMPF0100%7CPF0100
April, 2015
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