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Dave Embedded Systems ARM Cortex-A9 MPCore, Hardware Manual

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Dave Embedded Systems ARM Cortex-A9 MPCore Hardware Manual Download Page 69

A x e l   H a r d w a r e   M a n u a l

v . 1 . 0 . 4

SOM. The processor provides 4 MMC/SD/SDIO ports through 
the ULTRA Secured Digital Host Controller (USDHC), 
compliant with MMC V4.41, Secure Digital Memory Card 
Specification V3.00 and Secure Digital Input Output (SDIO) 
V3.00 specifications. The controller supports 1-bit / 4-bit SD 
and SDIO modes, 1-bit / 4-bit / 8-bit MMC modes. High capacity
SD cards (SDHC) are supported.

7.12.1 MMC/SD/SDIO1

The following table describes the interface signals:

Pin name

Conn.
Pin

Function

Notes

SD1_CD

J1.74

Card detection 
pin

If not used(for the 
embedded
memory),tie low to 
indicate there is a
card attached.

SD1_CLK

J1.99

Clock for 
MMC/SD/SDIO 
card

SD1_CMD

J1.97

CMD line

SD1_DATA0

J1.89

DATA0 line in all 
modes

Also used to detect 
busy state

SD1_DATA1

J1.91

DATA1 line in 
4/8-bit mode

Also used to detect 
interrupt in 1/4-
bit mode

SD1_DATA2

J1.93

DATA2 line or 
Read Wait in 4-bit
mode

Read Wait in 1-bit 
mode

SD1_DATA3

J1.95

DATA3 line in 
4/8-bit mode or
configured as 
card detection pin

May be configured as
card detection
pin in 1-bit mode

SD1_DATA4

J2.12

DATA4 line in 
8-bit mode, not 
used
in other modes

SD1_DATA5

J2.14

DATA5 line in 
8-bit mode, not 
used
in other modes

April, 2015

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Summary of Contents for ARM Cortex-A9 MPCore

Page 1: ...Solo Dual Quad ARM Cortex A9 MPCore CPU Module HARDWARE MANUAL info dave eu www dave eu DAVE Embedded Systems Line ...

Page 2: ...A x e l H a r d w a r e M a n u a l v 1 0 4 Page intentionally left blank April 2015 2 78 ...

Page 3: ... 3 NOR flash bank 19 3 4 NAND flash bank 20 3 5 Memory Map 20 3 6 Power supply unit 20 3 7 CPU module connectors 20 4 Mechanical specifications 22 4 1 Board Layout 22 4 2 Connectors 24 5 Power reset and control 25 5 1 Power Supply Unit PSU and recommended power up sequence 25 5 2 Reset scheme and control signals 29 5 2 1 CPU_PORn 30 5 2 2 Boot_Mode0 1 30 5 3 Voltage monitor 30 5 4 System boot 30 5...

Page 4: ...tput ports 54 7 4 1 LVDS 55 7 4 1 1LVDS0 55 7 4 1 2LVDS1 56 7 4 2 HDMI 57 7 4 3 Parallel RGB 58 7 4 4 MIPI DSI 59 7 5 Video Input ports 59 7 5 1 Parallel RGB 59 7 5 2 MIPI CSI 60 7 6 UARTs 60 7 6 1 UART1 60 7 6 2 UART2 60 7 6 3 UART3 61 7 6 4 UART4 61 7 6 5 UART5 62 7 7 SPI 62 7 7 1 ECSPI1 63 7 7 2 ECSPI2 63 7 7 3 ECSPI3 64 7 7 4 ECSPI4 64 7 7 5 ECSPI5 65 7 8 Raw NAND flash controller 65 7 9 I C 6...

Page 5: ...ication notes 78 Index of Tables Tab 1 Related documents 8 Tab 2 Abbreviations and acronyms used in this manual 8 Tab 3 CPU Memories Buses 14 Tab 4 Peripherals 15 Tab 5 Electrical Mechanical and Environmental Specifications 16 Tab 6 i MX6 comparison 19 Tab 7 DDR3 specifications 19 Tab 8 NOR flash specifications 20 Tab 9 NAND flash specifications 20 Illustration Index Fig 1 AXEL Powered by i MX6 pr...

Page 6: ...claimers DAVE Embedded Systems does not assume any responsibility about availability supplying and support regarding all the products mentioned in this manual that are not strictly part of the AXEL CPU module AXEL CPU Modules are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury DAVE Embedd...

Page 7: ...L module 1 6 Technical Support We are committed to making our product easy to use and will help customers use our CPU modules in their systems Technical support is delivered through email to our valued customers Support requests can be sent to support axel dave eu Software upgrades are available for download in the restricted access download area of DAVE Embedded Systems web site http www dave eu ...

Page 8: ...uals WT_VENDOR F REESCALE WT_FILE_FORMAT pdf WT_ASSET Documentatio n Tab 1 Related documents 1 8 Conventions Abbreviations Acronyms Abbreviation Definition i MX 6 APRM i MX 6 Application Processor Reference Manual IPU Image Processing Unit GPI General purpose input GPIO General purpose input and output GPO General purpose output PCB Printed circuit board RTC Real time clock SOM System on module TR...

Page 9: ... November 2013 First official release with XELK 1 0 0 1 0 1 January 2014 Minor fixes 1 0 2 August 2014 Minor fixes Fixed power up sequence diagram 1 0 3 November 2014 Minor fixes Released with XELK 2 0 0 1 0 4 April 2015 Minor fixes Added BOARD_PGOOD info Notes on NVCC_EIM_EXT Released with XELK 2 1 0 April 2015 9 78 ...

Page 10: ...tensive system level differentiation of new applications in many industry fields where high performance and extremely compact form factor 85mm x 50mm are key factors Smarter system designs are made possible following the trends in functionalities and interfaces of the new state of the art embedded products AXEL offers great computational power thanks to the rich set of peripherals the Scalable ARM...

Page 11: ...ns where RTOS and Linux work together on different cores Thanks to AXEL customers are going to save time and resources by using a powerful and scalable compact solution avoiding complexities on the carrier PCB AXEL is designed and manufactured according to DAVE Embedded Systems ULTRA Line specifications in order to guarantee premium quality and technical value for customers who require top perform...

Page 12: ...assive computing applications thanks to wide range DDR3 RAM memory up to 4GB Wide range PSU input from 2 8V to 4 5V High mechanical retention 100G shock thanks to 3x140pins and 4 screw holes Reduced carrier complexity dual CAN USB Ethernet GB PCIe SATA and native 3 3V I O Suitable for Asymmetric Multicore Processing A timing application thanks to on board 5ppm RTC April 2015 12 78 Fig 3 AXEL SOM t...

Page 13: ...A x e l H a r d w a r e M a n u a l v 1 0 4 2 2 Block Diagram April 2015 13 78 ...

Page 14: ...Specifications Options Graphics Controller 16 24 bit HD Display Port 1x HDMI 1 3 channel DDC 1x TFT RGB output port 1x MIPI DSI port 2x LVDS output ports 2D 3D Engines GPU2D cores for raster R2D Vivante GC320 and vector V2D Vivante GC355 graphics acceleration GPU3D core Vivante GC2000 for OpenGL OpenGL ES OpenVG OpenCL API acceleration Video capture 1x 20bit video input 1x MIPI CSI port Video proc...

Page 15: ...s 3x master and slave I C interfaces Audio 3x I S SSI AC97 interfaces Timers Enhanced Periodic Interrupt Timer General Purpose Timer RTC On board 3 5ppm DS3232 external battery powered Watchdog On board configurable timeout MAX6373 Debug JTAG IEEE 1149 1 Test Access Port CoreSight and Program Trace Macrocell PTM Tab 4 Peripherals Feature Specifications Options Supply Voltage 2 8 4 5V wide range in...

Page 16: ... a r e M a n u a l v 1 0 4 Feature Specifications Options Vibration tbd Connectors 3 x 140 pins 0 6mm pitch Connectors insertion remo val tbd Tab 5 Electrical Mechanical and Environmental Specifications April 2015 16 78 ...

Page 17: ...mentation of the ARM Cortex A9 MPCore which operates at speeds up to 1 2 GHz They include 2D and 3D graphics processors 1080p video processing and integrated power management As a result the i MX6 devices are able to serve a wide range of applications including Automotive driver assistance driver information and infotainment Multimedia centric smart mobile devices Instrument clusters and portable ...

Page 18: ...eaturing 1 Megabyte unified L2 cache shared by all CPU cores NEON MPE coprocessor General Interrupt Controller GIC with 128 interrupt support Snoop Control Unit SCU External memories interconnect Hardware accelerators including VPU Video Processing Unit Two IPUv3H Image Processing Unit version 3H 2D 3D Vector graphics accelerators Connectivity peripherals including PCIe SATA SD SDIO MMC Serial bus...

Page 19: ...B 64 bit 533 MHz 3D Vivante GC2000 2D Vivante GC320 Vector Vivante GC335 2x 2x Yes Tab 6 i MX6 comparison 3 2 DDR3 memory bank DDR3 SDRAM memory bank is composed by 4x 16 bit width chips resulting in a 64 bit combined width bank The following table reports the SDRAM specifications CPU connection Multi mode DDR controller MMDC Size min 512 MB Size max 4 GB Width 64 bit Speed 533 MHz Tab 7 DDR3 spec...

Page 20: ...detailed information please refer to chapter 2 Memory Maps of the i MX Applications Processor Reference Manual 3 6 Power supply unit AXEL as the other ULTRA Line CPU modules embeds all the elements required for powering the unit therefore power sequencing is self contained and simplified Nevertheless power must be provided from carrier board and therefore users should be aware of the ranges power ...

Page 21: ...ed peripheral interfaces according to AXEL pinout specifications For mechanical information please refer to Section 4 Mechanical specifications For pinout and peripherals information please refer to Sections 6 Pinout table and 7 Peripheral interfaces April 2015 21 78 ...

Page 22: ...teristics of the AXEL module Mechanical drawings are available in DXF format from the AXEL page on DAVE Embedded Systems website http www dave eu products som freescale imx6_axel u ltra 4 1 Board Layout The following figure shows the physical dimensions of the AXEL module April 2015 22 78 Fig 4 Board layout Top view ...

Page 23: ...4 Board height 50 8 mm Board width 83 8 mm Maximum components height is 2 mm top and 4 mm bottom PCB thickness is 1 9 mm The following figure highlights the maximum components heights on AXEL module April 2015 23 78 Fig 5 Board layout Side view ...

Page 24: ...rt number Hirose FX8C 140S SV Height 5 1 mm Length 48 6 mm Depth 4 0 mm Mating connectors Hirose FX8C 140P SV 5 mm board to board height Hirose FX8C 140P SV1 6 mm board to board height Hirose FX8C 140P SV2 7 mm board to board height Hirose FX8C 140P SV4 9 mm board to board height Hirose FX8C 140P SV6 11 mm board to board height April 2015 24 78 Fig 6 Connectors layout ...

Page 25: ...MEMS RTC PSU PMIC PF0100 E0 VGEN1 2V8 4V5 PMIC_PROG_GATE_CTRL VGEN 4 VGEN2 VGEN6 VSNVS SWBSTIN PWRON RESETBMCU STANDBY SDWNB INTB VDDOTP SCL SDA PMIC_LICELL VDDSOC DDR_1V5 1V2_ETH VDDHIGH_VPH VDDSOC_CAP VDDPU VDD_ARM23_CAP VDD_ARM01_CAP VGEN5_2V8 VDD_BUS_CAP VDD_SNVS_CAP VGEN3_2V5 NVCC_PLL_OUT SW4 VDDCORE NVCC_CSI_EXT NVCC_EIM_EXT NVCC_SD3_EXT NVCC_LCD_EXT RTC_VBAT VGEN1 VGEN2 VGEN4_1V8 VGEN6 SW4_...

Page 26: ...oard devices The typical power up sequence is the following 1 optional PMIC_LICELL is powered optional RTC_VBAT is powered 2 2V8 4V5 main power supply rail is powered 3 CPU_PORn active low is driven low 4 PMIC activates PMIC_VSNVS power output 5 PMIC_PWRON signal is pulled up unless carrier board circuitry keeps this signal low for any reason 6 PMIC transitions from OFF to ON state 7 PMIC initiate...

Page 27: ...ads NVCC_AXEL_I O_3 3V 1 8V might not be able to drive them properly In these cases a simple 2 input AND port can be used to address this issue The following picture depicts a principle schematic showing this solution VDD_SOM denotes the power rail used to power AXEL ULTRA SoM 5 1 2 Note on NVCC_EIM_EXT If the SPI NOR flash is mounted on the AXEL ULTRA SoM the NVCC_EIM_EXT input signal can t be co...

Page 28: ...main NVCC_LCD_EXT this rail powers MX6 s NVCC_LCD domain NVCC_AXEL_I O_3 3V 1 8V this output signal is used to indicate when carrier board s circuitry interfacing AXEL s I Os has to be powered up VGEN1 PMIC s VGEN1 regulator output this regulator is not used by any AXEL s internal load Output voltage can be selected by user VGEN2 PMIC s VGEN2 regulator output this regulator is not used by any AXEL...

Page 29: ...t regulator This regulator is not used by any AXEL s internal load Output voltage can be selected by user VDDCORE VDDSOC DDR_1V5 1V2_ETH VDDHIGH_VPH VDDSOC_CAP VDDPU VDD_ARM23_CAP VDD_ARM01_CAP VDGEN5_2V8 VDD_BUS_CAP VDD_SNVS_CAP VGEN3_2V5 NVCC_PLL_OUT these signals route power voltage generated by AXEL PSU These optional signals in the default configuration the pins are dedicated to other functio...

Page 30: ... CPU_PORn The following sources can assert this active low signal April 2015 30 78 i MX6 CPU POR CPU_PMIC_ON_REQ PMIC_ON_REQ PMIC_STB_REQ INTB SDWNB STANDBY PWRON RESETBMCU PMIC PF0100 E0 VOLTAGE MONITOR WDT PMIC_PWRON CPU_PORn CPU_PMIC_STBY_REQ PMIC_SDWNB PMIC_INTB WD_SET2 WD_SET1 WD_SET0 3 3V 10K 10K 10K 150 K 1K 10K 68K PMIC_VSNVS PMIC_VSNVS PMIC_VSNVS SPI NOR FLASH BOOT_MODE1 BOOT_MODE0 10K PM...

Page 31: ... pulled down with 10kOhm resistor and BOOT_MODE1 is pulled up to PMIC_VSNVS with 10kOhm resistor Different configurations are available on request For further details please refer to section 5 4 2 5 3 Voltage monitor The voltage monitor is a Linear Technology LTC2930 Configurable Six Supply Monitor with Adjustable Reset Timer Manual Reset 5 4 System boot The boot process begins at Power On Reset P...

Page 32: ...T_MODE 1 0 00 Boot from fuses 01 Serial downloader 10 Internal Boot 11 Reserved L1 I Cache disable bit BOOT_CFG3 7 0 L1 I Cache is enabled by ROM during the boot 1 L1 I Cache is disabled by ROM during the boot MMU L1 D Cache PL310 disable bit BOOT_CFG3 6 0 MMU L1 D Cache PL310 is enabled by ROM during the boot 1 MMU L1 D Cache PL310 is disabled by ROM during the boot Frequency Selection BOOT_CFG3 ...

Page 33: ...Table 5 9 page 359 In order to fully understand how boot works on AXEL platform please refer to chapter 8 System boot of the i MX6 APRM 5 4 2 Default boot configuration Default configuration for AXEL module is to boot from SPI NOR flash connected to eCSPI5 channel SS0 chip select with 3 Byte address mode This is achieved with the following bit mapping BOOT_MODE 1 0 10b Internal mode BOOT_CFG1 7 0 ...

Page 34: ...OT_CFG1 0 J2 3 EIM_DA0 BOOT_CFG1 1 J2 5 EIM_DA1 BOOT_CFG1 2 J2 7 EIM_DA5 BOOT_CFG1 3 J2 9 EIM_DA3 BOOT_CFG1 4 J2 11 EIM_DA4 BOOT_CFG1 5 J2 13 EIM_DA5 BOOT_CFG1 6 J2 15 EIM_DA6 BOOT_CFG1 7 J2 17 EIM_DA7 BOOT_CFG2 0 J2 19 EIM_DA8 BOOT_CFG2 1 J2 23 EIM_DA9 BOOT_CFG2 2 J2 25 EIM_DA10 BOOT_CFG2 3 J2 27 EIM_DA11 BOOT_CFG2 4 J2 29 EIM_DA12 BOOT_CFG2 5 J2 31 EIM_DA13 BOOT_CFG2 6 J2 33 EIM_DA14 BOOT_CFG2 7...

Page 35: ... corruption due power loss during upgrade or unrecoverable bug while developing a new U Boot feature the user will need sooner or later to recover bare metal restore the AXEL SOM without using the bootloader itself The following paragraphs introduce the available options For further information please refer to DAVE Embedded Systems Developers Wiki or contact the Technical Support Team 5 6 1 JTAG R...

Page 36: ...ultiplexing Most of the i MX 6 processor pins have multiple signal options These signal to pin and pin to signal options are selected by the input output multiplexer called IOMUX The IOMUX enables flexible IO multiplexing and is also used to configure other pin characteristics such as voltage level drive strength and hysteresis Each IO pad has default and up to seven alternate functions which are ...

Page 37: ...rly If the P does not μ provide a valid watchdog input transition before the timeout period expires the supervisor asserts a watchdog WDO output to signal that the system is not executing the desired instructions within the expected time frame The watchdog output pulse is used to reset the P WDI is is available on μ AXEL connectors as WDT_WDI J3 117 The MAX6373 watchdog timer is pin selectable and...

Page 38: ...onnectors Internal Connections Connections to the AXEL components CPU x pin connected to CPU PS processing system pad named x CAN x pin connected to the CAN transceiver PMIC x pin connected to the Power Manager IC LAN x pin connected to the LAN PHY SV x pin connected to voltage supervisor MTR pin connected to voltage monitors NOR pin connected to SPI NOR flash Ball pin Component ball pin number co...

Page 39: ... P20 NVCC_ J1 25 DISP0_DAT5 CPU DISP0_DAT5 R25 NVCC_ J1 27 DISP0_DAT6 CPU DISP0_DAT6 R23 NVCC_ J1 29 DISP0_DAT7 CPU DISP0_DAT7 R24 NVCC_ J1 31 DISP0_DAT8 CPU DISP0_DAT8 R22 NVCC_ J1 33 DISP0_DAT9 CPU DISP0_DAT9 T25 NVCC_ J1 35 DISP0_DAT10 CPU DISP0_DAT10 R21 NVCC_ J1 37 DISP0_DAT11 CPU DISP0_DAT11 T23 NVCC_ J1 39 DISP0_DAT12 CPU DISP0_DAT12 T24 NVCC_ J1 41 DGND DGND J1 43 DISP0_DAT13 CPU DISP0_DAT...

Page 40: ...F10 NVCC_ J1 87 USB_H1_VBUS CPU USB_H1_VBUS D10 NVCC_ J1 89 SD1_DAT0 CPU SD1_DAT0 A21 NVCC_ J1 91 SD1_DAT1 CPU SD1_DAT1 C20 NVCC_ J1 93 SD1_DAT2 CPU SD1_DAT2 E19 NVCC_ J1 95 SD1_DAT3 CPU SD1_DAT3 F18 NVCC_ J1 97 SD1_CMD CPU SD1_CMD B21 NVCC_ J1 99 SD1_CLK CPU SD1_CLK D20 NVCC_ J1 101 DGND DGND J1 103 SW2_1 8V 3 3V J1 105 ETH0_LED1 LAN LED1 PME_N1 17 J1 107 ETH0_LED2 LAN LED2 15 J1 109 DGND DGND J1...

Page 41: ...LVDS0_TX2_N V2 J1 14 LVDS0_TX2_P CPU LVDS0_TX2_P V1 J1 16 LVDS0_TX3_N CPU LVDS0_TX3_N W2 J1 18 LVDS0_TX3_P CPU LVDS0_TX3_P W1 J1 20 LVDS0_CLK_N CPU LVDS0_CLK_N V4 J1 22 LVDS0_CLK_P CPU LVDS0_CLK_P V3 J1 24 DGND DGND J1 26 CSI0_MCLK CPU CSI0_MCLK P4 J1 28 DGND DGND J1 30 CSI0_PIXCLK CPU CSI0_PIXCLK P1 J1 32 CSI0_VSYNC CPU CSI0_VSYNC N2 J1 34 CSI0_DATA_EN CPU CSI0_DATA_EN P3 J1 36 CSI0_DAT4 CPU CSI0...

Page 42: ..._6 I2C3_SDA CPU GPIO_6 T3 J1 86 GPIO_7 FLEXCAN1_H CPU GPIO_7 R3 J1 88 GPIO_8 FLEXCAN1_L CPU GPIO_8 R5 J1 90 DGND DGND J1 92 GPIO_9 CPU GPIO_9 T2 J1 94 GPIO_16 CPU GPIO_16 R2 J1 96 GPIO_17 CPU GPIO_17 R1 J1 98 GPIO_18 CPU GPIO_18 P6 J1 100 GPIO_19 CPU GPIO_19 P5 J1 102 KEY_COL0 ECSPI1_SCLK CPU KEY_COL0 W5 J1 104 KEY_ROW0 ECSPI1_MOSI CPU KEY_ROW0 V6 J1 106 KEY_COL1 ECSPI1_MISO CPU KEY_COL1 U7 J1 108...

Page 43: ...in Pin Name Internal Connections Ball pin Supply Group Type Voltage Note J2 1 DGND DGND J2 3 EIM_DA0 CPU EIM_DA0 L20 J2 5 EIM_DA1 CPU EIM_DA1 J25 J2 7 EIM_DA2 CPU EIM_DA2 L21 J2 9 EIM_DA3 CPU EIM_DA3 K24 J2 11 EIM_DA4 CPU EIM_DA4 L22 J2 13 EIM_DA5 CPU EIM_DA5 L23 J2 15 EIM_DA6 CPU EIM_DA6 K25 J2 17 EIM_DA7 CPU EIM_DA7 L25 J2 19 EIM_DA8 CPU EIM_DA8 L24 J2 21 DGND DGND J2 23 EIM_DA9 CPU EIM_DA9 M21 ...

Page 44: ...7 E25 J2 65 EIM_D28 CPU EIM_D28 G23 J2 67 EIM_D29 CPU EIM_D29 J19 J2 69 EIM_D30 CPU EIM_D30 J20 J2 71 EIM_D31 CPU EIM_D31 H21 J2 73 EIM_A16 CPU EIM_A16 H25 J2 75 EIM_A17 CPU EIM_A17 G24 J2 77 EIM_A18 CPU EIM_A18 J22 J2 79 EIM_A19 CPU EIM_A19 G25 J2 81 DGND DGND J2 83 EIM_A20 CPU EIM_A20 H22 J2 85 EIM_A21 CPU EIM_A21 H23 J2 87 EIM_A22 CPU EIM_A22 F24 J2 89 EIM_A23 CPU EIM_A23 J21 J2 91 EIM_A24 CPU ...

Page 45: ...OLTAGE J2 135 2V8 4V5 INPUT VOLTAGE J2 137 2V8 4V5 INPUT VOLTAGE J2 139 2V8 4V5 INPUT VOLTAGE J2 EVEN 2 140 Pin Pin Name Internal Connections Ball pi n Supply Group Type Voltage Note J2 2 NANDF_CS0_B CPU NANDF_CS0_B F15 J2 4 NANDF_CS1_B CPU NANDF_CS1_B C16 J2 6 NANDF_CS2_B CPU NANDF_CS2_B A17 J2 8 NANDF_CS3_B CPU NANDF_CS3_B D16 J2 10 DGND DGND J2 12 NANDF_D0 CPU NANDF_D0 A18 J2 14 NANDF_D1 CPU NA...

Page 46: ...D4_DATA6 CPU SD4_DATA6 B20 J2 58 SD4_DATA7 CPU SD4_DATA7 D19 J2 60 PMIC_SDWNB PMIC SDWNB 2 J2 62 TEST_MODE CPU TEST_MODE E12 J2 64 RTC_INTN SQW RTC INT SQW 3 J2 66 RTC_RSTN RTC RST 4 J2 68 RTC_32KHZ RTC 32KHZ 1 J2 70 DGND DGND J2 72 PMIC_INT_B PMIC INTB 1 J2 74 PMIC_PWRON PMIC PWRON 56 J2 76 CPU_ONOFF CPU CPU_ONOFF D12 J2 78 CPU_PORN CPU CPU_PORN C11 J2 80 CPU_PMIC_STBY_REQ CPU CPU_PMIC_STBY_REQ F...

Page 47: ..._LCD_EXT INTERNAL VOLTAGE SWITCH Please refer to section 5 1 J2 120 DGND DGND J2 122 PMIC_PROG_SCL J2 124 PMIC_PROG_SDA J2 126 2V8 4V5 INPUT VOLTAGE J2 128 2V8 4V5 INPUT VOLTAGE J2 130 2V8 4V5 INPUT VOLTAGE J2 132 2V8 4V5 INPUT VOLTAGE J2 134 2V8 4V5 INPUT VOLTAGE J2 136 2V8 4V5 INPUT VOLTAGE J2 138 2V8 4V5 INPUT VOLTAGE J2 140 2V8 4V5 INPUT VOLTAGE 6 3 Carrier board mating connector J3 J3 ODD 1 1...

Page 48: ... CPU MLB_DP A10 J3 45 DGND DGND J3 47 SATA_RXN CPU SATA_RXN A14 J3 49 SATA_RXP CPU SATA_RXP B14 J3 51 DGND DGND J3 53 SATA_TXN CPU SATA_TXN B12 J3 55 SATA_TXP CPU SATA_TXP A12 J3 57 DGND DGND J3 59 CPU_RGMII_TXC_CONN CPU RGMII_TXC D21 J3 61 DGND DGND J3 63 CPU_RGMII_TD0_CONN CPU RGMII_TD0 C22 J3 65 CPU_RGMII_TD1_CONN CPU RGMII_TD1 F20 J3 67 CPU_RGMII_TD2_CONN CPU RGMII_TD2 E21 J3 69 CPU_RGMII_TD3_...

Page 49: ...NET_RX_ER VDDSOC CPU ENET_RX_ER W23 J3 105 ENET_RXD0 DDR_1V5 CPU ENET_RXD0 W21 J3 107 ENET_RXD1 CPU ENET_RXD1 W22 J3 109 ENET_TXD0 BB_3 3V 2 5V CPU ENET_TXD0 U20 J3 111 ENET_TXD1 1V2_ETH CPU ENET_TXD1 W20 J3 113 KEY_COL4 ENET_CRS_DV VDDHIGH_VPH CPU KEY_COL4 T6 J3 115 KEY_ROW4 VDDSOC_CAP CPU KEY_ROW4 V5 J3 117 WDT_WDI VDDPU WDT WDI 1 J3 119 VDD_ARM23_CAP VGEN4_1 V8 J3 121 VDD_ARM01_CAP VGEN5_2 V8 V...

Page 50: ..._D3M CPU CSI_D3M F2 J3 30 CSI_D3P CPU CSI_D3P F1 J3 32 DGND DGND J3 34 DSI_CLK0M CPU DSI_CLK0M H3 J3 36 DSI_CLK0P CPU DSI_CLK0P H4 J3 38 DGND DGND J3 40 DSI_D0M CPU DSI_D0M G2 J3 42 DSI_DOP CPU DSI_DOP G1 J3 44 DGND DGND J3 46 DSI_D1M CPU DSI_D1M H2 J3 48 DSI_D1P CPU DSI_D1P H1 J3 50 DGND DGND J3 52 LVDS1_TX0_N CPU LVDS1_TX0_N Y1 J3 54 LVDS1_TX0_P CPU LVDS1_TX0_P Y2 J3 56 DGND DGND J3 58 LVDS1_TX1...

Page 51: ...DMI_D1N CPU HDMI_D1N J3 J3 96 HDMI_D1P CPU HDMI_D1P J4 J3 98 DGND DGND J3 100 HDMI_D2N CPU HDMI_D2N K3 J3 102 HDMI_D2P CPU HDMI_D2P K4 J3 104 DGND DGND J3 106 HDMI_CEC_IN CPU HDMI_DDCCEC K2 J3 108 HDMI_HPD CPU HDMI_HPD K1 J3 110 DGND DGND J3 112 CLK1_N CPU CLK1_N C7 J3 114 CLK1_P CPU CLK1_P D7 J3 116 DGND DGND J3 118 CLK2_N CPU CLK2_N C5 J3 120 CLK2_P CPU CLK2_P D5 J3 122 DGND DGND J3 124 PCIE_RXN...

Page 52: ...mented on the module The signals for each interface are described in the related tables The following notes summarize the column headers for these tables Pin name The symbolic name of each signal Conn Pin The pin number on the module connectors Function Signal description Notes This column summarizes configuration requirements and recommendations for each signal 7 1 Notes on pin assignment For fur...

Page 53: ...pendent Interface 2 negative pin ETH0_TXRX3_P J1 131 Media Dependent Interface 3 positive pin ETH0_TXRX3_M J1 129 Media Dependent Interface 3 negative pin RGMII_MDIO J1 137 Management Data Input Output RGMII_MDC J1 135 Management Data Clock input ETH0_INTn J3 95 Interrupt output ETH0_LED1 J1 105 Activity LED ETH0_LED2 J1 107 Link LED 7 3 USB AXEL provides two USB ports with integrated PHY one USB ...

Page 54: ...ctivity to displays and related processing synchronization and control Each IPU has two display ports each controlled by a DI module providing a connection to displays and external devices either directly parallel interface or via bridges MIPI LVDS HDMI Each IPU has 2 display ports up to four external ports can be active at any given time Additional asynchronous data flows can be sent though the p...

Page 55: ...nel output one input source splitted to 2 channels on output Separate 2 channel output 2 input sources from IPU The output LVDS port complies to the EIA 644 A standard 7 4 1 1 LVDS0 The following table describes the interface signals Pin name Conn Pin Function Notes LVDS0_DATA 0 _N J1 2 LVDS0 negative data 0 signal LVDS0_DATA 0 _P J1 4 LVDS0 positive data 0 signal LVDS0_DATA 1 _N J1 6 LVDS0 negati...

Page 56: ...a 1 signal LVDS1_TX1_P J3 60 LVDS1 positive data 1 signal LVDS1_TX2_N J3 64 LVDS1 negative data 2 signal LVDS1_TX2_P J3 66 LVDS1 positive data 2 signal LVDS1_TX3_N J3 76 LVDS1 negative data 3 signal LVDS1_TX3_P J3 78 LVDS1 positive data 3 signal LVDS1_CLK_N J3 70 LVDS1 negative clock signal LVDS1_CLK_P J3 72 LVDS1 positive clock signal 7 4 2 HDMI The HDMI interface available on AXEL is based on th...

Page 57: ...I negative data 0 HDMI_TX_DATA0_P J3 90 HDMI positive data 0 HDMI_TX_DATA1_N J3 94 HDMI negative data 1 HDMI_TX_DATA1_P J3 96 HDMI positive data 1 HDMI_TX_DATA2_N J3 100 HDMI negative data 2 HDMI_TX_DATA2_P J3 102 HDMI positive data 2 HDMI_TX_DDC_CEC J3 106 HDMI CEC signal HDMI_TX_DDC_SCL J1 116 J2 111 HDMI I2C clock signal HDMI_TX_DDC_SDA J1 118 J2 37 HDMI I2C data signal HDMI_TX_HPD J3 108 HDMI ...

Page 58: ...6 J1 27 Pixel data bit 6 DISP0_DAT7 J1 29 Pixel data bit 7 DISP0_DAT8 J1 31 Pixel data bit 8 DISP0_DAT9 J1 33 Pixel data bit 9 DISP0_DAT10 J1 35 Pixel data bit 10 DISP0_DAT11 J1 37 Pixel data bit 11 DISP0_DAT12 J1 39 Pixel data bit 12 DISP0_DAT13 J1 43 Pixel data bit 13 DISP0_DAT14 J1 45 Pixel data bit 14 DISP0_DAT15 J1 47 Pixel data bit 15 DISP0_DAT16 J1 49 Pixel data bit 16 DISP0_DAT17 J1 51 Pix...

Page 59: ...clock pair DSI_CLK0P J3 36 DSI_D0M J3 40 MIPI Display Differential data 0 pair DSI_D0P J3 42 DSI_D1M J3 46 MIPI Display Differential data 1 pair DSI_D1P J3 458 7 5 Video Input ports This section will be completed in a future version of this manual 7 5 1 Parallel RGB This section will be completed in a future version of this manual 7 5 2 MIPI CSI This section will be completed in a future version o...

Page 60: ... Ring indicator UART1_RTS J2 47 J3 13 Request to send UART1_RX_DATA J1 52 J3 23 Serial infrared data receive UART1_TX_DATA J1 48 J3 25 Serial infrared data transmit 7 6 2 UART2 The following table describes the interface signals Pin name Conn Pin Function Notes UART2_CTS J2 65 J3 5 J2 56 Clear to send UART2_RTS J2 67 J3 1 J2 54 Request to send UART2_RX_DATA J2 63 J1 88 J3 19 J2 52 Serial infrared ...

Page 61: ...a transmit 7 6 4 UART4 The following table describes the interface signals Pin name Conn Pin Function Notes UART4_CTS J1 64 Clear to send UART4_RTS J1 62 Request to send UART4_RX_DATA J1 56 J1 104 Serial infrared data receive UART4_TX_DATA J1 54 J1 102 Serial infrared data transmit 7 6 5 UART5 The following table describes the interface signals Pin name Conn Pin Function Notes UART5_CTS J1 68 J3 1...

Page 62: ...peripherals Transfer continuation function allows unlimited length data transfers 32 bit wide by 64 entry FIFO for both transmit and receive data Configurable Polarity and phase of the Chip Select SS and SPI Clock SCLK Direct Memory Access DMA support 7 7 1 ECSPI1 The following table describes the interface signals Pin name Conn Pin Function Notes ECSPI1_MISO J1 106 J1 40 J1 63 J2 39 Master data i...

Page 63: ...7 7 2 ECSPI2 The following table describes the interface signals Pin name Conn Pin Function Notes ECSPI2_MISO J1 48 J1 51 J2 97 Master data in slave data out ECSPI2_MOSI J1 46 J1 49 J2 117 Master data out slave data in ECSPI2_RDY J2 93 Data ready signal ECSPI2_SCLK J1 44 J1 55 J2 115 Clock signal ECSPI2_SS0 J1 52 J1 53 J2 99 Chip select 0 signal ECSPI2_SS1 J1 47 J2 95 Chip select 1 signal ECSPI2_S...

Page 64: ...ect 2 signal ECSPI3_SS3 J1 27 Chip select 3 signal 7 7 4 ECSPI4 The following table describes the interface signals Pin name Conn Pin Function Notes ECSPI4_MISO J2 51 Master data in slave data out ECSPI4_MOSI J2 65 Master data out slave data in ECSPI4_RDY J2 113 Data ready signal ECSPI4_SCLK J2 49 Clock signal ECSPI4_SS0 J2 47 J2 67 Chip select 0 signal ECSPI4_SS1 J2 93 Chip select 1 signal ECSPI4...

Page 65: ...PI5_SS3 J1 140 Chip select 3 signal 7 8 Raw NAND flash controller Raw NAND flash memory controller signals are routed to the connectors to connect an external flash NAND memory chip The following table describes the interface signals Pin name Conn Pin Function Notes NAND_ALE J2 36 Address latch enable signal NAND_CE0_B J2 2 Chip enable 0 signal NAND_CE1_B J2 4 Chip enable 1 signal NAND_CE2_B J2 6 ...

Page 66: ...Three I C channels are available on AXEL to provide an interface to other devices compliant with Philips Semiconductors Inter IC bus I2C bus specification version 2 1 The I C ports support standard mode up to 100K bits s and fast mode up to 400K bits s 7 9 1 I C1 The following table describes the interface signals Pin name Conn Pin Function Notes I2C1_SCL J1 46 J2 49 I2C clock I2C1_SDA J1 44 J2 65...

Page 67: ...tocol version 2 0 part B and supports bit rates up to 1 Mbit s 7 10 1 FLEXCAN1 FLEXCAN1 port is connected to on board transceiver TI SN65HVD232 which converts the single ended CAN signals of the controller to the differential signals of the physical layer When required the on board transceiver can be excluded by dedicated mount options Please contact our Sales Department for more information about...

Page 68: ... Conn Pin Function Notes FLEXCAN2_RX J3 115 J3 13 Receive data pin FLEXCAN2_TX J3 113 J3 11 Transmit data pin 7 11 JTAG The i MX6 provides debug access via a standard JTAG IEEE 1149 1 debug interface The following table describes the interface signals Pin name Conn Pin Function Notes JTAG_TDO J2 98 JTAG TDO JTAG_TDI J2 96 JTAG TDI JTAG_TMS J2 100 JTAG TMS JTAG_TCK J2 92 JTAG clock JTAG_VREF J2 94 ...

Page 69: ... Notes SD1_CD J1 74 Card detection pin If not used for the embedded memory tie low to indicate there is a card attached SD1_CLK J1 99 Clock for MMC SD SDIO card SD1_CMD J1 97 CMD line SD1_DATA0 J1 89 DATA0 line in all modes Also used to detect busy state SD1_DATA1 J1 91 DATA1 line in 4 8 bit mode Also used to detect interrupt in 1 4 bit mode SD1_DATA2 J1 93 DATA2 line or Read Wait in 4 bit mode Re...

Page 70: ...te protect detect If not used for the embedded memory tie low to indicate it s not write protected 7 12 2 MMC SD SDIO2 The following table describes the interface signals Pin name Conn Pin Function Notes SD2_CD J1 80 Card detection pin If not used for the embedded memory tie low to indicate there is a card attached SD2_CLK J1 132 Clock for MMC SD SDIO card SD2_CMD J1 128 CMD line SD2_DATA0 J1 134 ...

Page 71: ... SD2_DATA6 J2 24 DATA6 line in 8 bit mode not used in other modes SD2_DATA7 J2 26 DATA7 line in 8 bit mode not used in other modes SD2_LCTL J1 84 LED control used to drive an external LED Active high Fully controlled by the driver Optional output SD2_VSELECT J1 108 J1 114 IO power voltage selection signal SD2_WP J1 76 Card write protect detect If not used for the embedded memory tie low to indicat...

Page 72: ...ait in 1 bit mode SD3_DATA3 J3 17 DATA3 line in 4 8 bit mode or configured as card detection pin May be configured as card detection pin in 1 bit mode SD3_DATA4 J3 19 DATA4 line in 8 bit mode not used in other modes SD3_DATA5 J3 21 DATA5 line in 8 bit mode not used in other modes SD3_DATA6 J3 23 DATA6 line in 8 bit mode not used in other modes SD3_DATA7 J3 25 DATA7 line in 8 bit mode not used in o...

Page 73: ...SD4_DATA2 J2 46 DATA2 line or Read Wait in 4 bit mode Read Wait in 1 bit mode SD4_DATA3 J2 48 DATA3 line in 4 8 bit mode or configured as card detection pin May be configured as card detection pin in 1 bit mode SD4_DATA4 J2 52 DATA4 line in 8 bit mode not used in other modes SD4_DATA5 J2 54 DATA5 line in 8 bit mode not used in other modes SD4_DATA6 J2 56 DATA6 line in 8 bit mode not used in other ...

Page 74: ...E_TXM J3 130 PCIE Transmit Data Lane 0 PCIE_TXP J3 132 PCIE_RXM J3 124 PCIE Receive Data Lane 0 PCIE_RXP J3 126 7 14 SATA AXEL provides a Serial ATA II SATA II 3 0 Gbps controller with integrated PHY which supports all SATA power management features eSATA and hardware assisted native command queuing NCQ for up to 32 entries The following table describes the interface signals Connector Pin Pin name...

Page 75: ...on the GPIO peripheral can produce CORE interrupts The device contains eight GPIO blocks and each GPIO block is made up of 32 identical channels The device GPIO peripheral supports up to 256 3 3 V GPIO pins Each channel must be properly configured since GPIO signals are multiplexed with other interfaces signals For more information on how to configure and use GPIOs please refer to section 5 7 For ...

Page 76: ...le because in most cases this would lead to an over sized power supply unit Several configurations have been tested in order to provide figures that are measured on real world use cases instead Please note that AXEL platform is so flexible that it is virtually impossible to test for all possible configurations and applications on the market The use cases here presented should cover most of real wo...

Page 77: ... w a r e M a n u a l v 1 0 4 manual 8 3 2 Set 2 This section will be completed in a future version of this manual 8 4 Heat Dissipation This section will be completed in a future version of this manual April 2015 77 78 ...

Page 78: ... following documents available on DAVE Embedded Systems Developers Wiki Document Location Integration Guide http wiki dave eu index php Inte gration_guide_ 28Axel 29 Carrier board design guidelines http wiki dave eu index php Carr ier_board_design_guidelines_ 28SOM 29 April 2015 78 78 ...

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