dspblok™ 21469 User Manual
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JH5, JH7 – Data Bus
The data bus is split to two separate connectors, one for address and the other for data. The ADSP-21469
has an 8 bit data bus. Earlier dspbloks based on the ADSP-21369 supported a 32 bit data bus. This was
needed primarily to support wide SDRAM interfacing. The original JH6 connection on the dspblok 21369zx
board was used for the extended data bus. This is also why there are unused pins on JH5. If you are adapting
a dspblok 21369zx design to support the dspblok 21469, you should verify that these changes will not
impact your design. In most cases, this will not be an issue.
The address bus is also organized so that the MS# lines and the lower address lines are grouped together.
This allows a smaller receptacle to be used when the whole address space is not required.
JH6 – Link Port
The Link Port connections include 33 ohm series terminators as well as 10K pulldowns for LCLKx and
LACKx. The series terminators will have minimal effect when located on the receive side of a link port
connection, but are required on the driving end of a link port connection.
If you are connecting another non-dspblok device to a link port, make sure your circuit includes series
terminators at the driving end of any connection. These terminators are often available internally in FPGAs.
You should not supply additional terminators on the dspblok side of a connection.
Link ports circuits are fast so careful attention to pcb layout and/or cabling is essential. Consult a Danville
engineer if you have questions about this topic.
JH8 – dspBootloader Mode
JH8 supports the Danville dspBootloader. The dspBootloader allows you to upload your application and any
supporting files via a variety of different ports. If the connections are left open, the dspBootloader will
operate in its default setting. We recommend that you bring the mode pins out to an external configuration
header or a dip switch.
You should review the dspBootloader manual for detailed information.
