dspblok™ 21469 User Manual
Page 9
Clocks
The dspblok 21469 supports both internal and external clocking options. You can add a standard HC49 style
crystal to the board for internal clocking or you can supply an external clock. The configuration header (JH3)
allows any ADSP-21469 power-up clock configuration to be set.
Link Ports
The dspblok 21469 has two link ports available that can be used to interface to additional dspblok 21469
boards or may be used to connect to other external devices such as FPGAs.
Multiprocessor Configurations
The dspblok 21469 may be used as a coprocessor in a larger system. Perhaps the easiest way to
communicate with an external host to configure the secondary SPI port as a slave. The primary SPI port
remains configured as an SPI master so that it can manage local resources such as flash and EE memory as
well as other I/O devices.
Certainly, the Link Ports are available for multiprocessor systems. They are ideal where fast interprocessor
communications are required. Since clocks and data are always driven from the same source, clock skew is
minimized.
You can also use SPORTs for interprocessor communication. This can be a good approach for Blackfin –
SHARC combinations. It also works well for multichannel applications where you might use several dspbloks
to provide front end signal processing and combine into a consolidated TDM data stream. The results could
be routed to a central processor that manages the whole system and communicates to the outside world.
Reset
On power up, the dspblok 21469 is automatically held in reset until the 3.3V power supply is stable.
RESET# is active low and open drain. This means that an external device(s) may also reset the dspblok by
pulling the reset line low. External devices should not drive RESET# high since this can cause contention with
the on-board reset circuit. The external reset circuit is connected in a wired-OR configuration using an active
low – open drain configuration. A 74LVC125 or an open collector/drain transistor circuit are possibilities. You
do not need an additional pull up resistor.
Signal Levels
The dspblok 21469 uses standard 3.3V logic levels. These levels have become the defacto operating standard
for many years now. DO NOT use 5V logic when interfacing to the dspblok. The inputs are not 5V tolerant.
Most external devices requiring 5V TTL levels can be safely driven by the dspblok. If you have questions
concerning interfacing external devices, please contact Danville for suggestions.
Boot Options
All ADSP-21469 boot options are available via the configuration and programming header (JH3). These
include Master SPI (flash memory), Slave SPI (external host) or Link Port. The boot mode pins are pulled
passively to create a default boot mode of SPI Master.
