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Dallas Semiconductor DS21354L, Manual

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Dallas Semiconductor DS21354L Manual Download Page 9

DS21354 & DS21554

9 of 117

3.2  DOCUMENT REVISION HISTORY

Date

Notes

1-27-99

Initial release

1-28-99

Corrected TSYSCLK and RSYSCLK timing and added 4.096 MHz and 8.192 MHz
timing

2-3-99

Corrected definition and label of TUDR bit in the THIR register.

2-11-99

Correct address of IBO register in text.

4-1-99

Add Receive Monitor Mode section

4-15-99

Add section on Protected Interfaces

5-7-99

Correct pin # and description of FMS in JTAG section

7-29-99

Add list of tables and figures

9-14-99

Add 10uf cap to interface examples

9-23-99

Correct definition of DS* in pin description.

Summary of Contents for DS21354L

Page 1: ...700 C DS21354LN 400 C to 850 C DS21554L 00 C to 700 C DS21554LN 400 C to 850 C DESCRIPTION The DS21354 554 Single Chip Transceiver SCT contains all of the necessary functions for connection to E1 lin...

Page 2: ...ave Bus Operation Pins 23 4 1 6 Line Interface Pins 23 4 1 7 Supply Pins 24 5 PARALLEL PORT 24 5 1 Register Map 25 6 CONTROL ID AND TEST REGISTERS 29 6 1 Power Up Sequence 30 6 1 1 Synchronizatrion an...

Page 3: ...56 14 1 Hardware Scheme 57 14 2 Internal Register Scheme Based on Double Frame 57 14 3 Internal Register Scheme Based on CRC4 Multiframe 59 15 HDLC CONTROLLER FOR THE SA BITS OR DS0 60 15 1 General Ov...

Page 4: ...AL TIMING DIAGRAMS 88 19 1 Receive 88 19 2 Transmit 94 20 OPERATING PARAMETERS 103 21 AC TIMING PARAMETERS AND DIAGRAMS 104 21 1 Multiplexed Bus AC Characteristics 104 21 2 Non Multiplexed Bus AC Char...

Page 5: ...9 7 TRANSMIT SIDE TIMING 94 Figure 19 8 TRANSMIT SIDE BOUNDARY TIMING with elastic store disabled 95 Figure 19 9 TRANSMIT SIDE 1 544 MHz BOUNDARY TIMING with elastic store enabled 96 Figure 19 10 TRAN...

Page 6: ...ITERIA 42 Table 15 1 HDLC CONTROLLER REGISTER LIST 61 Table 16 1 LINE BUILD OUT SELECT IN LICR FOR THE DS21554 70 Table 16 2 LINE BUILD OUT SELECT IN LICR FOR THE DS21354 70 Table 16 3 TRANSFORMER SPE...

Page 7: ...CM data stream Signaling freezing Interrupt generated on change of signaling data 7 Improved receive sensitivity 0 dB to 43 dB 12 Per channel code insertion in both transmit and receive paths 8 Expand...

Page 8: ...clock The transmit side framer is totally independent from the receive side in both the clock requirements and characteristics Data off of a backplane can be passed through a transmit side elastic st...

Page 9: ...rrected definition and label of TUDR bit in the THIR register 2 11 99 Correct address of IBO register in text 4 1 99 Add Receive Monitor Mode section 4 15 99 Add section on Protected Interfaces 5 7 99...

Page 10: ...ceive path Receive Line I F Clock Data Recovery RRING RTIP Remote Loopback VCO PLL MCLK 8XCLK 8MCLK 8 192MHz Clock Synthesizer 32 768MHz 16 384 MHz XTALD RCLK RPOSO RNEGO RNEGI RPOSI TPOSI TNEGI TNEGO...

Page 11: ...8 RVDD Receive Analog Positive Supply 19 RVSS Receive Analog Signal Ground 20 RVSS Receive Analog Signal Ground 21 MCLK I Master Clock Input 22 XTALD O Quartz Crystal Driver 23 NC No Connect 24 RVSS R...

Page 12: ...4 Address Data Bus Bit 4 63 D5 AD5 I O Data Bus Bit 5 Address Data Bus Bit 5 64 D6 AD6 I O Data Bus Bit 6 Address Data Bus Bit 6 65 D7 AD7 I O Data Bus Bit 7 Address Data Bus Bit 7 66 A0 I Address Bus...

Page 13: ...Bus Bit 4 71 A5 I Address Bus Bit 5 72 A6 I Address Bus Bit 6 73 ALE AS A7 I Address Latch Enable Address Bus Bit 7 11 BTS I Bus Type Select 36 CI I Carry In 54 CO O Carry Out 75 CS I Chip Select 56...

Page 14: ...ve Carrier Loss 82 RCLK O Receive Clock 88 RCLKI I Receive Clock Input 89 RCLKO O Receive Clock Output 74 RD DS I Read Input Data Strobe 85 RDATA O Receive Data 97 RFSYNC O Receive Frame Sync 79 RLCLK...

Page 15: ...it Analog Signal Ground 77 WR R W I Write Input Read Write 22 XTALD O Quartz Crystal Driver 4 1 PIN FUNCTION DESCRIPTION 4 1 1 Transmit Side Pins Signal Name TCLK Signal Description Transmit Clock Sig...

Page 16: ...4 kHz to 20 kHz demand clock Sa bits for the TLINK input See Section 18 for details Signal Name TLINK Signal Description Transmit Link Data Signal Type Input If enabled this pin will be sampled on the...

Page 17: ...on the rising edge of TCLKO with the bipolar data out of the transmit side formatter This pin is normally tied to TNEGI Signal Name TCLKO Signal Description Transmit Clock Output Signal Type Output B...

Page 18: ...high or low during any of the 32 E1 channels Synchronous with RCLK when the receive side elastic store is disabled Synchronous with RSYSCLK when the receive side elastic store is enabled Useful for b...

Page 19: ...se the receive side elastic store See section 18 on page 115 for details on 4 096 MHz and 8 192 MHz operation using the Interleave Bus Option Signal Name RSIG Signal Description Receive Signaling Outp...

Page 20: ...Type Input Sampled on the falling edge of RCLKI for data to be clocked through the receive side framer RPOSI and RNEGI can be tied together for a NRZ interface Can be internally connected to RPOSO by...

Page 21: ...pe Input In non multiplexed bus operation MUX 0 serves as the data bus In multiplexed bus operation MUX 1 serves as a 8 bit multiplexed address data bus Signal Name A0 to A6 Signal Description Address...

Page 22: ...FMS 1 this pin is tied low internally Tie JTRST low if JTAG is not used and the framer is in DS21352 552 mode FMS low Signal Name JTMS Signal Description IEEE 1149 1 Test Mode Select Signal Type Input...

Page 23: ...of 2 048 MHz may be applied across MCLK and XTALD instead of a TTL level clock source at MCLK Leave open circuited if a TTL clock source is applied at MCLK Signal Name 8XCLK Signal Description Eight...

Page 24: ...hould be tied to the RVDD and DVDD pins Signal Name DVSS Signal Description Digital Signal Ground Signal Type Supply 0 0 volts Should be tied to the RVSS and TVSS pins Signal Name RVSS Signal Descript...

Page 25: ...11 R W Receive Control 2 RCR2 12 R W Transmit Control 1 TCR1 13 R W Transmit Control 2 TCR2 14 R W Common Control 1 CCR1 15 R W Test 1 TEST1 set to 00h 16 R W Interrupt Mask 1 IMR1 17 R W Interrupt M...

Page 26: ...g 13 RS13 3D R Receive Signaling 14 RS14 3E R Receive Signaling 15 RS15 3F R Receive Signaling 16 RS16 40 R W Transmit Signaling 1 TS1 41 R W Transmit Signaling 2 TS2 42 R W Transmit Signaling 3 TS3 4...

Page 27: ...mit Channel 10 TC10 6A R W Transmit Channel 11 TC11 6B R W Transmit Channel 12 TC12 6C R W Transmit Channel 13 TC13 6D R W Transmit Channel 14 TC14 6E R W Transmit Channel 15 TC15 6F R W Transmit Chan...

Page 28: ...RC23 97 R W Receive Channel 24 RC24 98 R W Receive Channel 25 RC25 99 R W Receive Channel 26 RC26 9A R W Receive Channel 27 RC27 9B R W Receive Channel 28 RC28 9C R W Receive Channel 29 RC29 9D R W R...

Page 29: ...ntrol registers Typically the control registers are only accessed when the system is first powered up Once the device has been initialized the control registers will only need to be accessed when ther...

Page 30: ...Bit 5 Bit 4 ID3 ID2 ID1 ID0 SYMBOL POSITION NAME AND DESCRIPTION T1E1 IDR 7 T1 or E1 Chip Determination Bit Set to 1 0 T1 chip 1 E1 chip Bit 6 IDR 6 Bit 6 See Table 6 1 Bit 5 IDR 5 Bit 5 See Table 6...

Page 31: ...rtain criteria that can cause a re synchronization These criteria are detailed in Table 6 2 Also see Figure 19 14 for a flow chart of the synchronization process SYNC RESYNC CRITERIA Table 6 2 FRAME O...

Page 32: ...lect Set to one to have RLCLK pulse at the Sa4 bit position set to zero to force RLCLK low during Sa4 bit position See Section 19 1 for timing details RBCS RCR2 2 Receive Side Backplane Clock Select 0...

Page 33: ...to zero to not source the Sa8 bit See Section 19 2 for timing details Sa7S TCR2 6 Sa7 Bit Select Set to one to source the Sa7 bit from the TLINK pin set to zero to not source the Sa7 bit See Section...

Page 34: ...S signaling mode RHDB3 CCR1 2 Receive HDB3 Enable 0 HDB3 disabled 1 HDB3 enabled RG802 CCR1 1 Receive G 802 Enable See Section 19 for details 0 do not force RCHBLK high during bit 1 of timeslot 26 1 f...

Page 35: ...R if CCR3 3 1 will override Receive Freeze Enable RFE See Section 10 2 for details 0 do not force a freeze event 1 force a freeze event RFE CCR2 0 Receive Freeze Enable See Section 10 2 for details 0...

Page 36: ...back function CCR3 4 Not Assigned Should be set to zero when written to RSRE CCR3 3 Receive Side Signaling Re Insertion Enable See Section 10 2 1 for details 0 do not re insert signaling bits into the...

Page 37: ...side formatter will be ignored Please see Figure 3 1 for more details 6 5 Local Loopback When CCR4 6 is set to a one the SCT will be forced into Local LoopBack LLB In this loopback data will continue...

Page 38: ...r Bit 0 LSB of the channel decode CCR6 COMMON CONTROL REGISTER 6 Address 1D Hex MSB LSB LIUODO CDIG LIUSI TCLKSRC RESR TESR SYMBOL POSITION NAME AND DESCRIPTION LIUODO CCR6 7 Line Interface Open Drain...

Page 39: ...latched fashion The Synchronizer Status Register contents are not latched This means that if an event or an alarm occurs and a bit is set to a one in any of the registers it will remain set until the...

Page 40: ...event occurs The INT pin will be allowed to return high if no other interrupts are present when the user reads the event bit that caused the interrupt to occur RIR RECEIVE INFORMATION REGISTER Address...

Page 41: ...ing for synchronization at the CRC4 level ITU G 706 suggests that if synchronization at the CRC4 level cannot be obtained within 400 ms then the search should be abandoned and proper action taken The...

Page 42: ...2 1 5 RUA1 receive unframed all ones less than three zeros in two frames 512 bits more than two zeros in two frames 512 bits O 162 1 6 1 2 RRA receive remote alarm bit 3 of non align frame set to one...

Page 43: ...ted or deleted a frame of data IMR1 INTERRUPT MASK REGISTER 1 Address 16 Hex MSB LSB RSA1 RDMA RSA0 RSLIP RUA1 RRA RCL RLOS SYMBOL POSITION NAME AND DESCRIPTION RSA1 IMR1 7 Receive Signaling All Ones...

Page 44: ...of these four counters are automatically updated on either one second boundaries CCR2 7 0 or every 62 5 ms CCR2 7 1 as determined by the timer in Status Register 2 SR2 4 Hence these registers contain...

Page 45: ...ot saturate The counter is disabled during loss of sync at either the FAS or CRC4 level it will continue to count if loss of multiframe sync occurs at the CAS level CRCCR1 CRC4 COUNT REGISTER 1 Addres...

Page 46: ...2 Address 04 Hex MSB LSB FAS11 FAS10 FAS9 FAS8 FAS7 FAS6 note 2 note 2 FASCR1 FAS5 FAS4 FAS3 FAS2 FAS1 FAS0 note 1 note 1 FASCR2 SYMBOL POSITION NAME AND DESCRIPTION FAS11 FASCR1 7 MSB of the 12 Bit F...

Page 47: ...that determines which transmit channel data will appear in the TDS0M register See Section 9 for details TCM3 CCR4 3 Transmit Channel Monitor Bit 3 TCM2 CCR4 2 Transmit Channel Monitor Bit 2 TCM1 CCR4...

Page 48: ...4 B5 RDS0M 3 Receive DS0 Channel Bit 5 B6 RDS0M 2 Receive DS0 Channel Bit 6 B7 RDS0M 1 Receive DS0 Channel Bit 7 B8 RDS0M 0 Receive DS0 Channel Bit 8 LSB of the DS0 channel last bit received 10 SIGNA...

Page 49: ...reported in SR1 6 A 1 RS2 7 1 Signaling Bit A for Channel 1 D 30 RS16 0 Signaling Bit D for Channel 30 Each Receive Signaling Register RS1 to RS16 reports the incoming signaling from two timeslots The...

Page 50: ...at is internal to the device The user can utilize the Transmit Multiframe bit in Status Register 2 SR2 5 to know when to update the signaling bits The bit will be set every 2 ms and the user has 2 ms...

Page 51: ...reeze by setting the RFF control bit CCR2 1 high Setting the RFF bit high causes the same freezing action as if a loss of synchronization carrier loss or slip has occurred The 2 multiframe buffer prov...

Page 52: ...from the E1 line to the backplane and is covered in Section 11 2 11 1 Transmit Side Code Generation In the transmit direction there are two methods by which channel data from the backplane can be ove...

Page 53: ...ced from the output of the receive side framer i e Per Channel Loopback see Figure 3 1 TIDR TRANSMIT IDLE DEFINITION REGISTER Address 2A Hex MSB LSB TIDR7 TIDR6 TIDR5 TIDR4 TIDR3 TIDR2 TIDR1 TIDR0 SYM...

Page 54: ...el one is shown see Table 5 1 for other register address MSB LSB C7 C6 C5 C4 C3 C2 C1 C0 RC1 80 SYMBOL POSITION NAME AND DESCRIPTION C7 RC1 7 MSB of the Code this bit is sent first to the backplane C0...

Page 55: ...LK pin high during this channel time TCBR1 TCBR2 TCBR3 TCBR4 TRANSMIT CHANNEL BLOCKING REGISTERS Address 22 to 25 Hex MSB LSB CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TCBR1 22 CH16 CH15 CH14 CH13 CH12 CH11 CH1...

Page 56: ...hether the elastic store is enabled or not If the elastic store is enabled then either CAS RCR1 7 0 or CRC4 RCR1 7 1 multiframe boundaries will be indicated via the RMSYNC output If the user selects t...

Page 57: ...eived in the Additional and International bit locations The RAF and RNAF registers are updated with the setting of the Receive Align Frame bit in Status Register 2 SR2 6 The host can use the SR2 6 bit...

Page 58: ...ignment Signal Bit 0 TAF 5 Frame Alignment Signal Bit 1 TAF 4 Frame Alignment Signal Bit 1 TAF 3 Frame Alignment Signal Bit 0 TAF 2 Frame Alignment Signal Bit 1 TAF 1 Frame Alignment Signal Bit 1 TAF...

Page 59: ...bit transmitted Please see the register descriptions below and Figure 19 15 for more details REGISTER ADDRESS HEX FUNCTION RSiAF 58 The eight Si bits in the align frame RSiNAF 59 The eight Si bits in...

Page 60: ...ertion Control Bit 0 do not insert data from the TSa7 register into the transmit data stream 1 insert data from the TSa7 register into the transmit data stream Sa8 TSaCR 0 Additional Bit 8 Insertion C...

Page 61: ...e user reads that bit The bit will be cleared when it is read and it will not be set again until the event has occurred again The real time bits report the current instantaneous conditions that are oc...

Page 62: ...POK bits and then read the FIFO a1 if CBYTE 0 then skip to step 5 a2 if CBYTE 1 then skip to step 7 b if REMPTY 1 then skip to step 6 5 repeat step 4 6 wait for interrupt skip to step 4 7 if POK 0 the...

Page 63: ...packet is written into the transmit FIFO at THFR This bit will be cleared by the HDLC controller when the last byte has been transmitted TZSD HCR 1 Transmit Zero Stuffer Defeat Overrides internal enab...

Page 64: ...he user to read the THIR register for details TMEND HSR 0 Transmit Message End Set when the transmit HDLC controller has finished sending a message The setting of this bit prompts the user to read the...

Page 65: ...the byte available for reading in the receive FIFO at RHFR is the last byte of a valid message and hence no abort was seen no overrun occurred and the CRC was correct CBYTE RHIR 1 Closing Byte Set whe...

Page 66: ...ed and will be cleared when read THFR TRANSMIT HDLC FIFO REGISTER Address B7 Hex MSB LSB HDLC7 HDLC6 HDLC5 HDLC4 HDLC3 HDLC2 HDLC1 HDLC0 SYMBOL POSITION NAME AND DESCRIPTION HDLC7 THFR 7 HDLC Data Bit...

Page 67: ...B5 RDC2 4 DS0 Bit 5 Suppress Enable Set to one to stop this bit from being used RDB4 RDC2 3 DS0 Bit 4 Suppress Enable Set to one to stop this bit from being used RDB3 RDC2 2 DS0 Bit 3 Suppress Enable...

Page 68: ...TDC2 3 DS0 Bit 4 Suppress Enable Set to one to stop this bit from being used TDB3 TDC2 2 DS0 Bit 3 Suppress Enable Set to one to stop this bit from being used TDB2 TDC2 1 DS0 Bit 2 Suppress Enable Set...

Page 69: ...see Figure 16 3 Normally the clock that is output at the RCLKO pin is the recovered clock from the E1 AMI HDB3 waveform presented at the RTIP and RRING inputs When no AMI signal is present at RTIP and...

Page 70: ...oss 1 2 step up 21dB 6 2 ohms 1 0 1 120 ohm w high return loss 1 2 step up 21dB 11 6 ohms NM Not Meaningful Return Loss value too low for significance See separate application note for details on E1 l...

Page 71: ...ld be placed from each leg of the crystal to ground as shown in Figure 16 2 Onboard circuitry adjusts either the recovered clock from the clock data recovery block or the clock applied at the TCLKI pi...

Page 72: ...ECTION Figure 16 2 JITTER TOLERANCE Figure 16 3 XTALD DS21554 354 C1 C2 2 048 MHz MCLK FREQUENCY Hz UNIT INTERVALS UIpp 1K 100 10 1 0 1 10 100 1K 10K 100K DS21354 DS21554 Tolerance 1 Minimum Tolerance...

Page 73: ...ON dB 100K J i t t e r A t t e n u a t i o n C u r v e ITUG 7XX ProhibitedArea ETS300011 TBR12 ProhibitedArea 40 0 0 1 0 2 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 1 1 1 2 0 TIME ns SCALED AMPLITUDE 50...

Page 74: ...or the 5 volt device and Figure 16 7 is an example for the 3 3 volt device In both examples fuses are used to provide protection against power line cross 470 ohm input resistors on the receive pair a...

Page 75: ...tage Protection and T1 Network Interface Design Criteria These applications notes are available from Dallas Semiconductor s Web site at www dalsemi com PROTECTED INTERFACE EXAMPLE FOR THE DS21354 Figu...

Page 76: ...nitor port isolation resistors Rm as shown in the Figure 16 8 The receiver of the DS21354 554 can provide gain to overcome the resistive loss of a monitor connection This is typically a purely resisti...

Page 77: ...TAP TAP Controller Instruction Register Bypass Register Boundary Scan Register Device Identification Register The DS21354 554 are enhanced versions of the DS2152 and are backward pin compatible The JT...

Page 78: ...e normally Run Test Idle The Run Test Idle is used between scan operations or during specific tests The Instruction register and test registers will remain idle Select DR Scan All test registers retai...

Page 79: ...evious state The controller will remain in this state while JTMS is LOW A rising edge on JTCLK with JTMS HIGH will put the controller in the Exit2 DR state Exit2 DR A rising edge on JTCLK with JTMS HI...

Page 80: ...r the Update IR state and terminate the scanning process Pause IR Shifting of the instruction shift register is halted temporarily With JTMS HIGH a rising edge on JTCLK will put the controller in the...

Page 81: ...troller to the Update IR state The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output Instructions supported by the DS21354 554 wi...

Page 82: ...tal outputs of the device will output data from the boundary scan parallel output while connecting the bypass register between JTDI and JTDO The outputs will not change during the CLAMP instruction HI...

Page 83: ...Bypass Register This is a single one bit shift register used in conjunction with the BYPASS CLAMP and HIGHZ instructions which provides a short path between JTDI and JTDO Identification Register The...

Page 84: ...GI I 57 40 TCLKI I 56 41 TCLKO O 55 42 TNEGO O 54 43 TPOSO O 44 DVDD 45 DVSS 53 46 TCLK I 52 47 TSER I 51 48 TSIG I 50 49 TESO O 49 50 TDATA I 48 51 TSYSCLK I 47 52 TSSYNC I 46 53 TCHCLK O 45 54 CO O...

Page 85: ...I 23 77 WR R W I 22 78 RLINK O 21 79 RLCLK O 80 DVSS 81 DVDD 20 82 RCLK O 83 DVDD 84 DVSS 19 85 RDATA O 18 86 RPOSI I 17 87 RNEGI I 16 88 RCLKI I 15 89 RCLKO O 14 90 RNEGO O 13 91 RPOSO O 12 92 RCHCL...

Page 86: ...nfigurations one SCT will be configured as the master device and the remaining SCTs will be configured as slave devices In the 4 096 MHz bus configuration there is one master and one slave In the 8 19...

Page 87: ...5 for details 18 2 Frame Interleave In frame interleave mode data is output to the PCM Data Out bus one frame at a time from each of the connected SCTs This mode is used only when all connected SCTs a...

Page 88: ...RCR1 6 0 2 RSYNC in multiframe mode RCR1 6 1 3 RLCLK is programmed to output just the Sa bits 4 RLINK will always output all 5 Sa bits as well as the rest of the receive data stream 5 This diagram as...

Page 89: ...K is programmed to mark the Sa4 bit in RLINK 3 Shown isa RNAF frame boundary 4 RSIG normally contains the CAS multiframe alignment nibble 0000 in channel 1 CHANNEL 32 CHANNEL 1 CHANNEL 2 CHANNEL 32 CH...

Page 90: ...nd 29 is dropped channel 2 from the E1 link is mapped to channel 1 of the T1 link etc and the F bit position is added forced to on1 2 RSYNC in the output mode RCR1 5 0 3 RSYNC in the input mode RCR1 5...

Page 91: ...mode RCR1 5 0 2 RSYNC is in the input mode RCR1 5 1 3 RCHBLK is programmed to block channel 1 4 RSIG normally contains the CAS multiframe alignment nibble 0000 in Channel 1 RSER CHANNEL 1 RCHCLK RCHB...

Page 92: ...LSB FRAMER 0 CHANNEL 1 R SIG FRAMER 3 CHANNEL 32 FRAMER 0 CHANNEL 1 MSB LSB FRAMER 1 CHANNEL 1 FRAMER 1 CHANNEL 1 3 R SER RSYNC R SIG R SER R SIG FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0...

Page 93: ...2 FR3CH1 32 FR0CH1 32 FR1CH1 32 FR2CH1 32 FR3CH1 32 FR0 CH1 32 FR1 CH1 32 R S E R LSB SYSCLK RSYNC FRAMER3 CHANNEL32 MSB LSB FRAMER0 CHANNEL1 R S IG FRAMER3 CHANNEL32 FRAMER0 CHANNEL1 MSB LSB FRAMER0...

Page 94: ...n multiframe mode TCR1 1 1 3 TLINK is programmed to source just the Sa4 bit 4 This diagram assumes both the CAS MF and the CRC4 MF begin with the TAF frame 5 TLINK and TLCLK are not synchronous with T...

Page 95: ...block channel 2 4 TLINK is programmed to source the Sa4 bit 5 The signaling data at TSIG during channel 1 is normally overwritten in the transmit formatter with the CAS MF alignment nibble 0000 6 Show...

Page 96: ...MHz BOUNDARY TIMING with elastic store enabled Figure 19 9 Notes 1 The F bit position in the TSER data is ignored 2 TCHBLK is programmed to block channel 24 LSB F MSB LSB MSB CHANNEL 1 CHANNEL 24 TSY...

Page 97: ...BOUNDARY TIMING with elastic store enabled Figure 19 10 Notes 1 TCHBLK is programmed to block channel 31 LSB F LSB MSB CHANNEL 1 CHANNEL 32 A B C D A B TSYSCLK TSER TSSYNC TSIG TCHCLK TCHBLK CHANNEL...

Page 98: ...B FRAMER 0 CHANNEL 1 TSIG FRAMER 3 CHANNEL 32 FRAMER 0 CHANNEL 1 MSB LSB FRAMER 1 CHANNEL 1 FRAMER 1 CHANNEL 1 3 TSER TSYNC TSIG TSER TSIG FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1...

Page 99: ...R3 CH1 32 FR0 CH1 32 FR1 CH1 32 FR2 CH1 32 FR3 CH1 32 FR0 CH1 32 FR1 CH1 32 TSER LSB SYSCLK TSYNC FRAMER 3 CHANNEL 32 MSB LSB FRAMER 0 CHANNEL 1 TSIG FRAMER 3 CHANNEL 32 FRAMER 0 CHANNEL 1 MSB LSB FRA...

Page 100: ...during timeslots 1 through 15 17 through 25 and bit 1 of timeslot 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 31 32 TS RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCH...

Page 101: ...C A SS ync C riteriaM et C A S S A 0 If C R C 4ison C C R 1 0 1 R LO S 1 If C A Sison C C R 1 3 0 P ow er U p Increm ent C R C 4 S yncC ounter C R C 4S A 0 C R C 4R esync C riteriaM et R IR 2 C A SM u...

Page 102: ...E R note 1 C C R 3 6 TC R 1 5 S ignalingB it InsertionC ontrol TIRFunctionS elect C C R 3 5 A IS G eneration 0 1 N O TE S 1 TC LKshouldbetiedtoR C LKandTSY N CshouldbetiedtoR FS YN Cfor datatobeproper...

Page 103: ...ONDITIONS 0 C to 70 C VDD 3 3V 5 for DS21354L 0 C to 70 C VDD 5 0V 5 for DS21554L 40 C to 85 C VDD 3 3V 5 for DS21354LN 40 C to 85 C VDD 5 0V 5 for DS21554LN PARAMETER SYMBOL MIN TYP MAX UNITS NOTES L...

Page 104: ...PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Cycle Time tCYC 200 ns Pulse Width DS low or RD high PWEL 100 ns Pulse Width DS high or RD low PWEH 100 ns Input Rise Fall times tR tF 20 ns R W Hold Time tRW...

Page 105: ...MUX 1 Figure 21 1 INTEL BUS WRITE TIMING BTS 0 MUX 1 Figure 21 2 ASH PW tCYC tASD tASD PW PW EH EL t t t t t t AHL CH CS ASL ASED CS AD0 AD7 DHR tDDR ALE RD WR ASH PW tCYC tASD tASD PW PW EH EL t t t...

Page 106: ...4 DS21554 106 of 117 MOTOROLA BUS AC TIMING BTS 1 MUX 1 Figure 21 3 tASD ASH PW t t ASL AHL tCS tASL t t t DSW DHW tCH t t t DDR DHR RWH tASED PWEH tRWS AHL PWEL tCYC AS DS AD0 AD7 write AD0 AD7 read...

Page 107: ...UNITS NOTES Set Up Time for A0 to A7 Valid to CS Active t1 0 ns Set Up Time for CS Active to either RD WR or DS Active t2 0 ns Delay Time from either RD or DS Active to Data Valid t3 75 ns Hold Time f...

Page 108: ...21 4 INTEL BUS WRITE AC TIMING BTS 0 MUX 0 Figure 21 5 AddressValid DataValid A0toA7 D0toD7 WR CS RD 0nsmin 0nsmin 75nsmax 0nsmin 5nsmin 20nsmax t1 t2 t3 t4 t5 Address Valid A0 to A7 D0 to D7 RD CS W...

Page 109: ...OTOROLA BUS WRITE AC TIMING BTS 1 MUX 0 Figure 21 7 Address Valid DataValid A0 to A7 D0 to D7 R W CS DS 0ns min 0ns min 75ns max 0ns min 5ns min 20ns max t1 t2 t3 t4 t5 Address Valid A0 to A7 D0 to D7...

Page 110: ...s ns 3 4 5 6 RSYSCLK Pulse Width tSH tSL 50 50 ns ns RSYNC Set Up to RSYSCLK Falling tSU 20 tSH 5 ns RSYNC Pulse Width tPW 50 ns RPOSI RNEGI Set Up to RCLKI Falling tSU 20 ns RPOSI RNEGI Hold From RCL...

Page 111: ...DATA RSIG RCHCLK RCHBLK RSYNC RLCLK RLINK tD1 Notes 1 RSYNC is in the output mode RCR1 5 0 2 RLCLK will only pulse high during Sa bit locations as defined in RCR2 no relationship between RLCLK and RSY...

Page 112: ...SIDE AC TIMING Figure 21 9 t F t R tD3 1 tD4 tD4 tD4 t tSU HD 2 RSER RSIG RCHCLK RCHBLK RSYNC RSYNC Notes 1 RSYNCis in theoutput mode RCR1 5 0 2 RSYNCis in theinput mode RCR1 5 1 RSYSCLK SL t tSP SH t...

Page 113: ...DS21354 DS21554 113 of 117 RECEIVE LINE INTERFACE AC TIMING Figure 21 10 t F t R RPOSI RNEGI RCLKI CL t tCP CH t tSU tHD tDD RPOSO RNEGO RCLKO LL t tLP LH t...

Page 114: ...ns ns 1 2 3 4 TSYSCLK Pulse Width tSH tSL 50 50 ns ns TSYNC or TSSYNC Set Up to TCLK or TSYSCLK falling tSU 20 tCH 5 or tSH 5 ns TSYNC or TSSYNC Pulse Width tPW 50 ns TSER TSIG TDATA TLINK TPOSI TNEG...

Page 115: ...1 TSYNC is in the output mode TCR1 0 1 2 TSYNC is in the input mode TCR1 0 0 3 TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled 4 TCHCLK and TCHBLK are sync...

Page 116: ...LK CO t t SL t SH SP TSSYNC TCHBLK tD3 tD3 t t tSU HD SU tHD Notes 1 TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled 2 TCHCLK and TCHBLK are synchro...

Page 117: ...DS21354 DS21554 117 of 117 22 MECHANICAL DESCRIPTION...

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