DS21354 & DS21554
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Signal Name:
ALE(AS)/a7
Signal Description:
Address Latch Enable(Address Strobe) or A7
Signal Type:
Input
In non–multiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus
operation (MUX = 1), serves to de-multiplex the bus on a positive–going edge.
Signal Name:
WR*(R/W*)
Signal Description:
Write Input(Read/Write)
Signal Type:
Input
WR* is an active low signal.
4.1.4 JTAG Test Access Port Pins
Signal Name:
JTRST*
Signal Description:
IEEE 1149.1 Test Reset
Signal Type:
Input
This signal is used to asynchronously reset the test access port controller. At power up, JTRST* must be
toggled from low to high. This action will set the device into JTAG DEVICE ID mode enabling the test
access port features. This pin has a 10k pull up resistor. When FMS=1, this pin is tied low internally.
Tie JTRST* low if JTAG is not used and the framer is in DS21352/552 mode (FMS low).
Signal Name:
JTMS
Signal Description:
IEEE 1149.1 Test Mode Select
Signal Type:
Input
This pin is sampled on the rising edge of JTCLK and is used to place the test access port into the various
defined IEEE 1149.1 states. This pin has a 10k pull up resistor.
Signal Name:
JTCLK
Signal Description:
IEEE 1149.1 Test Clock Signal
Signal Type:
Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge.
Signal Name:
JTDI
Signal Description:
IEEE 1149.1 Test Data Input
Signal Type:
Input
Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pull
up resistor.
Signal Name:
JTDO
Signal Description:
IEEE 1149.1 Test Data Output
Signal Type:
Output
Test instructions and data are clocked out of this pin on the falling edge of JTCLK. If not used, this pin
should be left unconnected.
