Daewoo DP-42GM, Service Manual

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Description Of Each BLOCK
(4)ROM & ROM Controller Block
- ROM contains Reverse Gamma Correction Table , Weight Conversion Table , APL
Table and so on. Rom Controller Block generate Address & Control signal for receiving
these data from ROM
(5)PISO(Parallel Input Serial Output) Block
- Load 10 pixels per each R,G,B data with parallel type and shift them with serial type in order
of Weight ( LSB first ). These shifted data is stored in Internal Memory of A500K270(ID2)
with based on DCLK(33.5MHz). After that, those data go into External Frame Memory
(SDRAM) in order of Weight with based on CLK50M. In other words, PISO Block execute
three steps Data Load Data Shift & Internal Memory Write Internal Memory Read &
External SDRAM Write successively. To process with real time, there are three PISO
Blocks.
(6)SDRAM & SDRAM Control Block
- Generate Address/Control signals for SDRAM. There are 2 SDRAMs (64M 32-bit SDRAM),
which store 1 Frame s R,G,B data in order of Weight respectively to process with real time.
(7)Data Interface Block
- R,G,B data ouput from SDRAM is stored by line in Data Interface Block. These data is output
in order matched by Data Driver IC(Z Driver IC) s input sequence. Our PDP has 853 Data
Lines per each R,G,B, and need 853*3=2559 bit s storage. To process with real time,
actually need 2559*2=5118 bit s storage.
3. PDP Driving Timing Control
(1)X-SUS Driving Control Signal Block
- Generate Control Signals to drive X-SUS PCB. There are 6 Control Signals as follows.
- X_SUSH, X_SUSL, X_ERH, X_ERL, X_HIGH, X_NSHELF
(2)Y-SUS Drving Control Signal Block
- Generate Control Signals to drive Y-SUS PCB & Scan Drvier IC. There are 12 Control Signals
as follows.
- Y_SUSH, Y_SUSL, Y_ERH, Y_ERL, Y_SC20_2, Y_SC20_3, Y_SC21_7, Y_SC21_9,
Y_BLK, Y_CLK, Y_SI1, Y_SI2
(3)Z Driving Control Signal Block
- Generate Control Signals to drive DATA COF (Z Driver IC). There are 8 Control Signals as
follows.
- Z1_CLK1, Z1_CLK2, Z2_CLK1, Z2_CLK2, Z1_BLK, Z1_STB, Z2_BLK, Z2_STB