Daewoo DP-42GM, Service Manual

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Description Of Each BLOCK
4-2-3. DIGITAL PCB
ID1
1st_chip(A500K180)
ID2
2nd_chip(A500K270)
ID3 & ID4
RGB DATA [0:3]
Inverse Gamma
&
Dithering
APL
Detection
ROM
(M27C1024)
ROM
Controller
ID33
PISO
PDP Driving
Timing Controller
SDRAM
Controller
SDRAM
(64M x 2)
Data Interface
Weight
Conversion
X Driver Control Signal Y Driver Control Signal
Z Driver Control Signal
Z Driver Data Signal
: Data Flow
: Control Address Flow
: ROM Data Flow
<DSP-4280GM Digital B/D Block Diagram>
1. Digital PCB s Main Part
(1)Actel FPGA A500K180-PQ208 : 1 EA
- Location No. : ID1
- Power : Internal 2.5V, I/O 3.3V
- Package : PQFP 208
- Typical Gates : 150,000
- User I/O : 164
(2)Actel FPGA A500K270-BG456 : 1 EA
- Location No. : ID2
- Power : Internal 2.5V, I/O 3.3V
- Package : BGA 456
- Typical Gates : 215,000
- User I/O : 362
(3)SDRAM( K4S643232E-TC70 86pin TSOP ) : 2 EA
- Location No. : ID3~4
- Power : 3.3V
- Size : 64 M ( 512K * 32 bit * 4 Banks )