FM33256B
Document Number: 001-86213 Rev. *C
Page 19 of 39
0Bh
Watchdog Control
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
WDST4
WDST3
WDST2
WDST1
WDST0
WDST(4:0)
Watchdog StartTime. Sets the starting time for the watchdog window timer with 25 ms (max.) resolution. The
window timer allow independent leading and trailing edges (start and end of window) to be set. New watchdog timer
settings are loaded when the timer is restarted by writing the 1010b pattern to WR(3:0). Nonvolatile, read/write.
Watchdog StartTime
WDST4
WDST3
WDST2
WDST1
WDST0
0 ms (default)
0
0
0
0
0
(min.)
(max.)
7.5 ms
25 ms
0
0
0
0
1
15 ms
50 ms
0
0
0
1
0
22.5 ms
75 ms
0
0
0
1
1
.
.
.
.
150 ms
500 ms
1
0
1
0
0
157.5 ms
525 ms
1
0
1
0
1
165 ms
550 ms
1
0
1
1
0
.
.
.
.
217.5 ms
725 ms
1
1
1
0
1
225 ms
750 ms
1
1
1
1
0
232.5 ms
775 ms
1
1
1
1
1
0Ah
Watchdog Restart
D7
D5
D4
D3
D2
D1
D0
-
-
-
WR3
WR2
WR1
WR0
WR(3:0)
Watchdog Restart. Writing a pattern 1010b to WR(3:0) restarts the watchdog timer. The upper nibble contents do
not affect this operation. Writing any pattern other than 1010b to WR(3:0) has no effect on the watchdog.
Write-only.
09h
Watchdog Flags
D7
D6
D5
D4
D3
D2
D1
D0
EWDF
-
POR
LB
-
-
-
-
EWDF
Early Watchdog Timer Fault Flag: When a watchdog restart occurs too early (before the programmed watchdog
StartTime), the RST pin is driven LOW and this flag is set. It must be cleared by the user. Note that both EWDF
and POR could be set if both reset sources have occurred since the flags were cleared by the user.
Battery-backed, read/write.
LWDF
Late Watchdog Timer Fault Flag: When either a watchdog restart occurs too late (after the programmed watchdog
EndTime) or no restart occurs, the RST pin is driven LOW and this flag is set. It must be cleared by the user. Note
that both LWDF and POR could be set if both reset sources have occurred since the flags were cleared by the
user. Battery-backed, read/write.
Table 7. Register Description
(continued)
Address
Description
