FM33256B
Document Number: 001-86213 Rev. *C
Page 7 of 39
If the power-fail comparator is not used, the PFI pin should be
tied to either V
DD
or V
SS
. Note that the PFO output will drive to
V
DD
or V
SS
as well.
Event Counter
The FM33256B offers the user a nonvolatile 16-bit event counter.
The input pin CNT has a programmable edge detector. The CNT
pin clocks the counter. The counter is located in registers
0E-0Fh. When the programmed edge polarity occurs, the
counter will increment its count value. The register value is read
by setting the RC bit (register 0Dh, bit 3) to ‘1’. This takes a
snapshot of the counter byte allowing a stable value even if a
count occurs during the read. The register value can be written
by first setting the WC bit (register 0Dh, bit 2) to ‘1’. The user then
may clear or preset the counter by writing to registers 0E-0Fh.
Counts are blocked when the WC bit is set, so the user must
clear the bit to allow counts.
The counter polarity control bit is CP (register 0Dh, bit 0). When
CP is ‘0’, the counter increments on a falling edge of CNT, and
when CP is set to ‘1’, the counter increments on a rising edge of
CNT. The polarity bit CP is nonvolatile.
The counter does not wrap back to zero when it reaches the limit
of 65,535 (FFFFh). Care must be taken prior to the rollover, and
a subsequent counter reset operation must occur to continue
counting.
There is also a control bit that allows the user to define the
counter as nonvolatile or battery-backed. The counter is
nonvolatile when the NVC bit (register 0Dh, bit 7) is logic 1 and
battery-backed when the NVC bit is logic 0. Setting the counter
mode to battery-backed allows counter operation under V
BAK
(as
well as V
DD
) power. The lowest operating voltage for
battery-backed mode is 2.0 V. When set to "nonvolatile" mode,
the counter operates only when V
DD
is applied and is above the
V
TP
voltage.
The event counter may be programmed to detect a tamper event,
such as the system's case or access door being opened. A
normally closed switch is tied to the CNT pin and the other
contact to the case chassis, usually ground. The typical solution
uses a pull-up resistor on the CNT pin and will continuously draw
battery current. The FM33256B chip allows the user to invoke a
polled mode, which occasionally samples the pin in order to
minimize battery drain. It internally tries to pull the CNT pin up
and if open circuit will be pulled up to a V
IH
level, which will trip
the edge detector and increment the event counter value. Setting
the POLL bit (register 0Dh, bit 1) places the CNT pin into this
mode. This mode allows the event counter to detect a rising edge
tamper event but the user is restricted to operating in
battery-backed mode (NVC = ‘0’) and using rising edge detection
(CP = ‘1’). The CNT pin is polled once every 125 ms. The
additional average I
BAK
current is less than 20 nA. The polling
timer circuit operates from the RTC, so the oscillator must be
enabled for this to function properly.
In the polled mode, the internal pull-up circuit can source a
limited amount of current. The maximum capacitance (switch
open circuit) allowed on the CNT pin is 100 pF.
Serial Number
A memory location to write a 64-bit serial number is provided. It
is a writeable nonvolatile memory block that can be locked by the
user once the serial number is set. The 8 bytes of data and the
lock bit are all accessed via unique opcodes for the RTC and
Processor Companion registers. Therefore the serial number
area is separate and distinct from the memory array. The serial
number registers can be written an unlimited number of times,
so these locations are general purpose memory. However once
the lock bit is set, the values cannot be altered and the lock
cannot be removed. Once locked the serial number registers can
still be read by the system.
The serial number is located in registers 10h to 17h. The lock bit
is SNL (register 18h, bit 7). Setting the SNL bit to a ‘1’ disables
writes to the serial number registers, and the SNL bit cannot be
cleared.
Figure 6. Comparator as a Power-Fail Warning
Figure 7. Event Counter
+
-
1.5 V ref
Regulator
V
DD
FM33256B
CAL/PFO
PFI
To MCU
NMI input
16-bit Counter
CNT
CP
Figure 8. Polled Mode on CNT pin Detects Tamper
CNT
FM33256B
125 ms
< 100 pF
V
BAK
