FM33256B
Document Number: 001-86213 Rev. *C
Page 10 of 39
Trickle Charger
To facilitate capacitor backup, the V
BAK
pin can optionally
provide a trickle charge current. When the VBC bit (register 18h,
bit 3) is set to a '1', the V
BAK
pin will source approximately 80 µA
until V
BAK
reaches V
DD
. This charges the capacitor to V
DD
without an external diode and resistor charger. There is also a
Fast Charge mode which is enabled by the FC bit (register 18h,
bit 2). In this mode the trickle charger current is set to
approximately 1 mA, allowing a large backup capacitor to charge
more quickly.
In the case where no backup supply is used, the V
BAK
pin should
be tied to V
SS
and VBC bit cleared.
Note
Systems using lithium batteries should clear the VBC bit to
‘0’ to prevent battery charging. The V
BAK
circuitry includes an
internal 1 K
Ω
series resistor as a safety element. The trickle
charger is UL Recognized.
Calibration
When the CAL bit in register 00h is set to a '1', the clock enters
calibration mode. The FM33256B employs a digital method for
calibrating the crystal oscillator frequency. The digital calibration
scheme applies a digital correction to the RTC counters based
on the calibration settings, CALS and CAL(4:0). In calibration
mode (CAL = ‘1’), the ACS pin is driven with a 512 Hz (nominal)
square wave and the alarm is temporarily unavailable. Any
measured deviation from 512 Hz translates into a timekeeping
error. The user measures the frequency and writes the
appropriate correction value to the calibration register. The
correction codes are listed in the table below. For convenience,
the table also shows the frequency error in ppm. Positive ppm
errors require a negative adjustment that removes pulses.
Negative ppm errors require a positive correction that adds
pulses. Positive ppm adjustments have the CALS (sign) bit set
to ‘1’, whereas negative ppm adjustments have CALS = ‘0’. After
calibration, the clock will have a maximum error of ±2.17 ppm or
±0.09 minutes per month at the calibrated temperature.
The user will not be able to see the effect of the calibration setting
on the 512 Hz output. The addition or subtraction of digital pulses
occurs after the 512 Hz output.
The calibration setting is stored in F-RAM so it is not lost should
the backup source fail. It is accessed with bits CAL(4:0) in
register 01h. These bits can be written when the CAL bit is set to
a ‘1’. To exit the calibration mode, the user must clear the CAL
bit to a logic ‘0’. When the CAL bit is ‘0’, the ACS pin will revert
to the function according to
Table 2
.
Crystal Type
The crystal oscillator is designed to use a 6 pF/12.5 pF crystal
without the need for external components, such as loading
capacitors. The FM33256B device has built-in loading capacitors
that are optimized for use with 6 pF crystals, but which work well
with 12.5 pF crystals. For either crystal, no additional external
loading capacitors are required nor suggested.
If a 32.768 kHz crystal is not used, an external oscillator may be
connected to the FM33256B.
Layout Recommendations
The X1 and X2 crystal pins employ very high impedance circuits
and the oscillator connected to these pins can be upset by noise
or extra loading. To reduce RTC clock errors from signal
switching noise, a guard ring should be placed around these
pads and the guard ring grounded. High speed SPI traces should
be routed away from the X1/X2 pads. The X1 and X2 trace
lengths should be less than 5 mm. The use of a ground plane on
the backside or inner board layer is preferred. See layout
example. Red is the top layer, green is the bottom layer.
Figure 12. Layout Recommendations
Layout for Surface Mount Crystal
(red = top layer, green = bottom layer)
Layout for Through Hole Crystal
(red = top layer, green = bottom layer)
CS
SO
CN T
V
BA K
X2
X1
V
SS
CS
SO
CN T
V
BA K
X2
X1
V
SS
