Cypress EX-USB FX3, Programmer'S Manual

Page: 25 / 192

FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 25
FX3 Overview
Figure 3-2. Interconnect Fabric
To allow implementation of an AHB system without the use of tri-state drivers and to facilitate
concurrent read/write operations, separate read and write data buses are required. The minimum
data bus width is specified as 32 bits, but the bus width can be increased for realizing higher
bandwidths.
3.3 Memory
In addition to the ARM core's tightly coupled instruction and data memories, a 512 KB general
purpose internal System memory is available in FX3. The system SRAM is implemented using 64- or
128-bit wide SRAM banks, which run at full CPU clock frequency. Each bank may be built up from
narrow SRAM instances for implementation specific reasons. A Cypress-proprietary high-
performance memory controller translates a stream of AHB read and writes requests into SRAM
accesses to the SRAM memory array. This controller also manages power and clock gating for the
memory array. The memory controller is capable of achieving full 100% utilization of the SRAM array
(meaning 1 read or 1 write at full width each cycle). CPU accesses are done 64 or 128 bit at a time to
SRAM and then multiplexed/demultiplexed as 2/4 32-bit accesses on the CPU AHB bus. The
controller does not support concurrent accesses to multiple different banks in memory.
ARM926EJS
M
S
AHB
Bridge
AHB
Bridge
ARM AHB Bus-I
ARM AHB Bus-D
System Bus
AHB
Slave
Interface
Internal Memory
Unit (Bus Slave)
M
M M S
Peripheral-2
DMA section
(Bus Master)
Peripheral-2
Reg section
(Bus Slave)
Peripheral-1
DMA section
(Bus Master)
Peripheral-1
Reg section
(Bus Slave)
DMA bus
MMIO bus
AHB
Master
Interface
AHB
Master
Interface
AHB
Slave
Interface
AHB
Slave
Interface
AHB
Bridge
M
S
S
M
S
AHB
Bridge
The block that is attached to the
bus at this point is the master
The block that is attached to the
bus at this point is the slave
Key
M
S
AHB
Master
Interface
M