Cypress EX-USB FX3, Programmer'S Manual

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FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 113
FX3 Serial Peripheral Register Access
9.1.3
UART Registers
The FX3 device implements a UART block that can communicate with other UART controllers at dif-
ferent baud rates and supports different communication parameters, parity settings, and flow control.
This section documents the UART related configuration and status registers.
9.1.3.1 UART_CONFIG register
This register specifies UART communication parameters such as data width, stop bits, parity config-
uration etc.
Name
Width
(bits)
Address Description
UART_CONFIG 32 0xE0000800 Configuration and modes register
UART_STATUS 32 0xE0000804 Status register
UART_INTR 32 0xE0000808 Interrupt status register
UART_INTR_MASK 32 0xE000080C Interrupt mask register
UART_EGRESS_DATA 32 0xE0000810 Write data register
UART_INGRESS_DATA 32 0xE0000814 Read data register
UART_SOCKET 32 0xE0000818 Socket selection register
UART_RX_BYTE_COUNT 32 0xE000081C Receive byte count register
UART_TX_BYTE_COUNT 32 0xE0000820 Transmit byte count register
UART_ID 32 0xE0000BF0 Block ID register
UART_POWER 32 0xE0000BF4 Power and reset control register
Bits Field Name
HW
Access
SW
Access
Default
Value
Description
0 RX_ENABLE R RW 0
0: Receiver disabled, ignore incoming data
1: Receiver enabled
1 TX_ENABLE R RW 1
0: Transmitter disabled, do not transmit data
1: Transmitter enabled
2 LOOP_BACK R RW 0
0: No effect
1: Connect the value being transmitted to the
receive buffer. Disable external transmit and
receive.
3 PARITY R RW 0
0: No parity
1: Include parity bit
4 PARITY_ODD R RW 0
0: Even Parity
1: Odd parity.
This is only relevant when PARITY=1 and
PARITY_STICKY=0
5 PARITY_STICKY R RW 0
0: Computed parity
1: Sticky parity
This is only relevant when PARITY=1
6 TX_STICKY_BIT R RW 0
Use this bit as the parity bit when sticky parity
is enabled.
This mechanism is used to implement mark
and space parity.
7 RX_STICKY_BIT R RW 0
Expected value of RX parity when sticky parity
is turned on.