Cypress EX-USB FX3, Programmer'S Manual

Page: 133 / 192

FX3 Programmers Manual, Doc. # 001-64707 Rev. *C 133
FX3 P-Port Register Access
10.2.2 PP_INIT Register
P-Port reset and power control. This register is used for reset and power control and determines the
endian orientation of the P-port.
Bits Name HW SW Default Description
0 POR RW R 1
Indicates system woke up through a power-
on-reset or RESET# pin reset sequence. If
firmware does not clear this bit it will stay 1
even through software reset, standby and
suspend sequences. This bit is a shadow bit
of GCTL_CONTROL.
1 SW_RESET RW R 0
Indicates system woke up from a software
induced hard reset sequence (from
GCTL_CONTROL.HARD_RESET_N or
PP_INIT.HARD_RESET_N). If firmware does
not clear this bit it will stay 1 even through
standby and suspend sequences. This bit is a
shadow bit of GCTL_CONTROL.
2 WDT_RESET RW R 0
Indicates system woke up from a watchdog
timer induced hard reset (see
GCTL_WATCHDOG_CS). If firmware does
not clear this bit it will stay 1 even through
standby and suspend sequences. This bit is a
shadow bit of GCTL_CONTROL.
3 WAKEUP_PWR RW R 0
Indicates system woke up from standby mode
(see architecture spec for details). If firmware
does not clear this bit it will stay 1 even
through suspend sequences. This bit is a
shadow bit of GCTL_CONTROL.
4 WAKEUP_CLK RW R 0
Indicates system woke up from suspend state
(see architecture spec for details). If firmware
does not clear this bit it will stay 1 even
through standby sequences. This bit is a
shadow bit of GCTL_CONTROL.
10 CPU_RESET_N R RW 1
Software clears this bit to effect a CPU reset
(aka reboot). No other blocks or registers are
affected. The CPU will enter the boot ROM,
that will use the WARM_BOOT flag to deter-
mine whether to reload firmware.
Unlike the same bit in GCTL_CONTROL, the
software needs to explicitly clear and then set
this bit to bring the internal CPU out of reset.
It is permissible to keep the ARM CPU in
reset for an extended period of time (although
not advisable).
11 HARD_RESET_N R
RW0
C
1
Software clears this bit to effect a global hard
reset (all blocks, all flops). This is equivalent
to toggling the RESET pin on the device. This
function is also available to internal firmware
in GCTL_CONTROL.
15 BIG_ENDIAN R RW 0
0: P-Port is Little Endian
1: P-Port is Big Endian