Cypress EX-USB FX3 Programmer'S Manual Download

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FX3 Programmers Manual

Doc. # 001-64707 Rev. *C

Cypress Semiconductor

198 Champion Court

San Jose, CA 95134-1709

Phone (USA): 800.858.1810

Phone (Intnl): 408.943.2600

http://www.cypress.com

Summary of Contents for EX-USB FX3

Page 1: ...FX3 Programmers Manual Doc 001 64707 Rev C Cypress Semiconductor 198 Champion Court San Jose CA 95134 1709 Phone USA 800 858 1810 Phone Intnl 408 943 2600 http www cypress com...

Page 2: ...able license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom soft ware and or firmware in support of lice...

Page 3: ...Classes 18 2 2 USB 3 0 Differences and Enhancements over USB 2 0 18 2 2 1 USB 3 0 Motivation 18 2 2 2 Protocol Layer 19 2 2 3 Link Layer 21 2 2 4 Physical Layer 21 2 2 5 Power Management 22 2 3 Refere...

Page 4: ...Power Management 73 5 2 8 Low Level DMA 73 6 FX3 APIs 75 7 FX3 Application Examples 77 7 1 DMA examples 77 7 1 1 cyfxbulklpauto AUTO Channel 77 7 1 2 cyfxbulklpautosig AUTO_SIGNAL Channel 77 7 1 3 cyf...

Page 5: ...bspiregmode SPI in Register Mode 81 7 3 8 cyfxusbspidmamode SPI in DMA Mode 81 7 3 9 cyfxusbspigpiomode SPI using GPIO 81 7 3 10 cyfxusbi2sdmamode I2S in DMA Mode 81 7 4 UVC examples 82 7 4 1 cyfxuvci...

Page 6: ...Q signaling 138 10 4 Transferring Data into and out of Sockets 139 10 4 1 Bursting and DMA_WMARK 139 10 4 3 Short Transfer Partial Buffer 141 10 4 4 Short Transfer Zero Length Buffers 142 10 4 5 Long...

Page 7: ...FX3 Programmers Manual Doc 001 64707 Rev C 7 Contents 13 1 3 CYUSB NET Programmer s reference 189 13 1 4 Cy Control Center 190 14 GPIF II Designer 191...

Page 8: ...8 FX3 Programmers Manual Doc 001 64707 Rev C Contents...

Page 9: ...ed USB 2 0 OTG controller enables applications that need dual role usage scenarios It has 512 KB of on chip SRAM for code and data It supports serial peripherals such as UART SPI I2C and I2S that enab...

Page 10: ...ts code examples which illustrate the API usage and the firmware framework FX3 Application Structure on page 85 describes the FX3 application framework and usage model for FX3 APIs FX3 Serial Peripher...

Page 11: ...names and reference documentation Read about the sourcefile hex file in the PSoC Designer User Guide Bracketed Bold Displays keyboard commands in procedures Enter or Ctrl C File Open Represents menu p...

Page 12: ...12 FX3 Programmers Manual Doc 001 64707 Rev C Introduction...

Page 13: ...drives The host owns the bus and is responsible for detecting a device as well as initiating and managing transfers between various devices Hubs are devices that have one upstream port and multiple do...

Page 14: ...can exist for the configuration and the maximum power a particular configuration uses Only one configuration of a device can be active at any time Each function of the device has an interface descript...

Page 15: ...on Figure 2 1 USB Packets A regular pay load data transfer requires at least three packets Token Data and Ack Figure 2 1 illustrates a USB OUT transfer Host traffic is shown in solid shading while dev...

Page 16: ...g transmission To detect this each side host and device maintains a data toggle bit which is toggled between data packet transfers The state of this internal toggle bit is compared with the PID that a...

Page 17: ...ces must respond to address zero when first attached 2 The device responds to the request by sending ID data back to the host to identify itself 3 The host sends a Set Address request which assigns a...

Page 18: ...attempt to simplify the development of new devices commonly used device functions were identified and nominal drivers were developed to support these devices The host uses the information in the clas...

Page 19: ...ave undergone some changes and enhancements These are discussed in the sections to follow Link Management packets are sent between links to communicate link level issues such as link configuration and...

Page 20: ...t packet which also contains the next packet number in the sequence This process continues until all the packets are transmitted unless an endpoint responds with an error during the transaction In tra...

Page 21: ...r command queuing The concept of streams enable more powerful mass storage protocols A typical communication link consists of a command OUT pipe an IN and OUT pipe with multiple data streams and a sta...

Page 22: ...d signaling In fact the Idle mode can be exited with an LFPS transmission from either the host or device The USB 3 0 standard also introduces the Function Suspend feature which enables the power manag...

Page 23: ...erface GPIF II provides connection to any processor ASIC DSP or FPGA There is 512 kB of on chip SRAM for code and data There are also low performance peripherals such as UART SPI I2 C and I2S to commu...

Page 24: ...erals using low power macro cell functions while providing a high bandwidth communication link between elements that are involved in majority of the transfers This multi master high bandwidth intercon...

Page 25: ...into SRAM accesses to the SRAM memory array This controller also manages power and clock gating for the memory array The memory controller is capable of achieving full 100 utilization of the SRAM arra...

Page 26: ...ware based interrupt management system that handles interrupt vectoring priority masking and timing providing a real time interrupt status The PL192 VIC supports 32 active high interrupt sources the I...

Page 27: ...is implemented by using the ARM9EJ S core embedded within the ARM926EJ S processor The ARM9EJ S core has hardware that eases debugging at the lowest level The debug extensions allow to stall the core...

Page 28: ...breakpoints The EmbeddedICE RT logic interacts with the external logic logic outside the CPU subsystem using the debug interface In addition it can be programmed for example setting a breakpoint using...

Page 29: ...N is the bus width chosen In fixed SCK mode however WS toggles every thirty second SCK edge In this mode the audio sample is zero padded to 32 bit FX3 supports word at a time SGL_LEFT_DATA SGL_RIGHT_D...

Page 30: ...place start repeated or stop bits between the bytes and can also define the master s behavior on receiving either a NAK or ACK for bytes in the preamble In applications such as EEPROM reads this grea...

Page 31: ...oftware software can signal a request to send using the SW_RTS field of the block and monitor the block s CTS_STAT signal Transmission starts when a 0 level start bit is transmitted and ends when a 1...

Page 32: ...etween 4 and 32 bits By default the Tx and Rx registers shift data to the left big endian This can be reversed if necessary The SSPOL input sets the polarity of the SSN Slave Select signal The CPOL in...

Page 33: ...Pins Several pins of FX3 can function as General Purpose IO s Each of these pins is multiplexed to support other functions interfaces like UART SPI and so on By default pins are allocated in larger g...

Page 34: ...0 GPIF IO 0 GPIF IO 0 GPIF IO 0 GPIF IO 0 Blk IO 1 GPIF IO 1 GPIF IO 1 GPIF IO 1 GPIF IO 1 GPIF IO 1 GPIF IO 1 Blk IO 29 GPIF IO 29 GPIF IO 29 GPIF IO 29 GPIF IO 29 GPIF IO 29 GPIF IO 29 Blk IO 30 NC...

Page 35: ...ble as GPIOs FX3 Pin I O selection n 0 to 60 Override block IO as simple GPIO pin n False Override block IO as complex GPIO pin n False Override block IO as simple GPIO pin n True Override block IO as...

Page 36: ...4 D4 D4 D4 D4 D4 GPIF IO 5 D5 A5 D5 A5 D5 A5 D5 A5 D5 A5 D5 D5 D5 D5 D5 GPIF IO 6 D6 A6 D6 A6 D6 A6 D6 A6 D6 A6 D6 D6 D6 D6 D6 GPIF IO 7 D7 A7 D7 A7 D7 A7 D7 A7 D7 A7 D7 D7 D7 D7 D7 GPIF IO 8 D8 A8 D8...

Page 37: ...0 A30 C14 D30 C14 A2 GPIF IO 45 D31 A31 C13 D31 C13 A3 GPIF IO 29 C12 C12 C12 C12 C12 C12 A0 C12 A4 C12 A4 C12 A0 C12 A8 GPIF IO 28 C11 C11 C11 C11 C11 C11 A1 C11 A5 C11 A5 C11 A1 C11 A9 GPIF IO 27 C1...

Page 38: ...iminating the need for a separate slave FIFO interface A large state space 256 states to enable more complex pipelined signaling protocols A wider data path supporting 32 bit mode in addition to 16 an...

Page 39: ...pheral loop back between USB end points are collectively referred to as DMA in FX3 Figure 3 11 shows a logical paths of data flow however in practice all DMA data flows through the System memory as sh...

Page 40: ...X3 do not present themselves as a single large source or sink for data rather the external host or device gets to index the data to from different addresses In practice though physical address and dat...

Page 41: ...isters which indicate the status of the socket such as number of bytes transferred over the socket current sub buffer being filled or emptied location of the current buffer in memory and no buffer ava...

Page 42: ...S Kernel etc E 0010000 E 001 FFFF E 0020000 E002 FFFF EFFF0000 EFFFFFFF 00000020 RESET N A FFFFFFFF F0000000 UNDEF INSTR SW INT ABORT PREF ABORT DATA RESERVED IRQ FIQ 00000000 00000004 00000008 000000...

Page 43: ...of the PMODE pins is scanned to determine the boot mode and enable the appropriate interface block GPIF I2 C or USB For example the code may reside in the EEPROM attached to FX3 s I2 C bus In some ca...

Page 44: ...kHz external clock source is used for low power operation during standby In the absence of a 32 kHz input clock source the application can derive this from the reference clock produced by the oscilla...

Page 45: ...DIV_CLK _OUT CLKIN SEL_CLK _DIV N 0 DIV_CLK _OUT CLKIN SEL_CLK _DIV N 0 DIV_CLK _OUT CLKIN SEL_CLK _DIV N 0 DIV_CLK _OUT Xtal Osc CLKIN SEL_CLK _DIV N 0 DIV_CLK _OUT USB2PHY PLL CLKIN CLKOUT_480 CLKO...

Page 46: ...system is in normal mode The usual clock gating techniques in peripherals minimize the overall power consumption On detecting prolonged periods of inactivity the chip can be forced to enter the suspen...

Page 47: ...y the CPU goes through a reset the boot loader senses the warm boot mode and restores the system to its original state after loading back the configuration values including the firmware resume point f...

Page 48: ...48 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Overview...

Page 49: ...h as charger detection USB device host detection and endpoint configuration Interface to different master slave peripherals on the GPIF interface Connect to serial peripherals UART SPI GPIO I2 C I2S S...

Page 50: ...nents 4 3 FX3 Firmware Stack Powerful and flexible applications can be rapidly built using FX3 firmware framework and FX3 API libraries 4 3 1 Firmware Framework The firmware or application framework h...

Page 51: ...included in the FX3 SDK This stack includes the Cypress generic USB 3 0 driver APIs that expose the driver interfaces and application examples Each of these components are described in brief in this...

Page 52: ...s an integrated development environment IDE with compiler linker assembler and JTAG debugger 4 5 2 GPIF II Designer GPIF II Interface Design Tool is a Windows application provided to FX3 customers as...

Page 53: ...e set up according to the device type and the internal I O matrix is configured accordingly Clock setup The firmware framework sets the CPU clock at startup MMU and cache management The FX3 device doe...

Page 54: ...setup is complete this function is only expected to initialize any application data 3 The main function which is the C programming language entry for the firmware is invoked next The FX3 device is in...

Page 55: ...tion tightly coupled memory which gives sin gle cycle access This area is recommended for interrupt handlers and exception vectors for reducing interrupt latencies The first 256 bytes are reserved for...

Page 56: ...MODE STACK BASE 0x1000 0C00 SIZE 0x0400 SVC MODE STACK BASE 0x1000 1000 SIZE 0x1000 D TCM BASE 0x1000 0000 SIZE 0x2000 DATA AREA BASE 0x4003 0000 SIZE 0x8000 If no compiler heap 0x7000 if compiler he...

Page 57: ...03000 LENGTH 0x2D000 DATA ORIGIN 0x40030000 LENGTH 0x8000 SECTIONS 0x100 vectors CYU3P_ITCM_SECTION I TCM 0x40003000 text text rodata constdata emb_text CYU3P_EXCEPTION_VECTORS _etext SYS_MEM 0x400300...

Page 58: ..._STACK Base 0x10001000 Size 4KB If for any reason the application needs to modify this it can be done before invoking CyU3PDeviceInit inside the main function Changing this is not recommended 5 1 3 3...

Page 59: ...red for programming the different blocks of the FX3 The APIs provide for the following Programming each of the individual blocks of the FX3 device GPIF USB and serial interfaces Programming the DMA en...

Page 60: ...D pin This makes the USB device visible to a connected USB host and the enumeration continues Setup Request By default the USB driver handles all Setup Request packets that are issued by the host The...

Page 61: ...l data transfers across the USB are done by the DMA engine The simplest way of using the DMA engine is by creating DMA channels Each USB endpoint is mapped to a DMA socket The DMA channels are created...

Page 62: ...fers Setup abort data transfers on endpoints 5 2 1 6 USB OTG Mode APIs The USB OTG Mode APIs are used to configure the USB port functionality and peripheral detection These include APIs for Start and...

Page 63: ...rovision to switch to different states These state switches are initiated through specific calls The GPIF II can be configured as a master or as a slave When the GPIF II is configured as a master GPIF...

Page 64: ...the serial interface driver to program the UART functionality The UART is first initialized and then the UART configurations such as baud rate stop bits parity and flow control are set After this is...

Page 65: ...ace that does not require DMA Two modes of GPIO pins are available with FX3 devices Simple and Complex GPIOs Simple GPIO provides software controlled and observable input and output capability only Co...

Page 66: ...are defined to address common data transfer scenarios 5 2 4 1 Automatic Channels An automatic DMA channel is one where the data flows between the producer and consumer uninterrupted when the channel i...

Page 67: ...fication cannot be used to modify the contents of the DMA buffer Figure 5 5 Auto Channel with Signaling Many to One Auto Channel This channel is defined as DMA_TYPE_AUTO_MANY_TO_ONE is a variation of...

Page 68: ...y Modify the data in the buffers provided the data size itself is not modified In manual channels the CPU FX3 firmware itself can be the producer or the consumer of the data Manual channels have a low...

Page 69: ...plication when a specified default is one number of buffers are transferred Callback function invoked at end of transaction Producer Ingress Socket Consumer Egress Socket D0_P D1_P D2_P Dn_P Incoming...

Page 70: ...nel It is defined by more than one valid producer socket a valid consumer socket and a predetermined amount of buffering each of these is a user programmable parameter This type of channel is used whe...

Page 71: ...els are handled by the channel functions The amount of buffering required size of buffer and number of buffers must be specified at the time of channel creation If channel creation is successful the r...

Page 72: ...Event get and set Timer Timer creation and deletion Timer start and stop Timer modify Get set time current time in ticks 5 2 6 Debug Support Debug support is provided in the form of a debug logging sc...

Page 73: ...supported on the block where each socket serves as the access point for one of the data flows Each socket has a set of registers that identify the other end of the data flow and control parameters suc...

Page 74: ...74 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Firmware...

Page 75: ...C 75 6 FX3 APIs The FX3 APIs consist of APIs for programming the main hardware blocks of the FX3 These include the USB GPIF II DMA and the Serial I Os Please refer to the corresponding sections of th...

Page 76: ...76 FX3 Programmers Manual Doc 001 64707 Rev C FX3 APIs...

Page 77: ...klpauto AUTO Channel This example demonstrates the use of DMA AUTO channels The data received in EP1 OUT is looped back to EP1 IN without any firmware intervention This type of channel provides the ma...

Page 78: ...thout any firmware intervention The buffers received on EP1 IN will be of the fashion EP1 OUT Buffer 0 EP1 OUT Buffer 2 and so on and buffers received on EP2 IN will of the fashion EP1 OUT Buffer 1 EP...

Page 79: ...s that are meant to be a programming guide for the following Setting up the descriptors and USB enumeration USB endpoint configuration USB reset and suspend handling 7 2 1 cyfxbulklpautoenum USB Enume...

Page 80: ...fault debug logging in all other examples are done through the UART This example shows how any consumer socket can be used to log FX3 debug data 7 2 9 cyfxbulklpauto_cpp Bulkloop Back Example using C...

Page 81: ...filled up DMA mode of operation is useful when there is large amount of data to be transferred 7 3 5 cyfxusbi2cregmode I2C in Register Mode This example demonstrates the use of I2C master in register...

Page 82: ...T to the slave FIFO egress socket and also transmits the data received on slave FIFO ingress socket to EP1 IN This requires a slave FIFO master capable of reading and writing data to be attached to FX...

Page 83: ...from an actual microphone but is read from an SPI flash connected to the FX3 device The audio data is then streamed over isochronous endpoints to the USB host 7 8 Two Stage Booter Example boot_fw A si...

Page 84: ...84 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Application Examples...

Page 85: ...contains the GPIF II descriptors for the 16 bit and 32 bit Slave FIFO interface 2 cyfxslfifousbdscr c This file contains the USB descriptors 3 cyfxslfifosync h This file contains the defines used in c...

Page 86: ...not visible to the user As part of the linker options the entry point is be specified as the CyU3PFirmwareEntry function The firmware entry function performs the following actions 1 Invalidates the c...

Page 87: ..._main mov R0 0 ldr R1 _bss_start ldr R2 _bss_end 1 cmp R1 R2 strlo R0 R1 4 blo 1b b main In this function only two actions are performed The BSS area is cleared The control is transferred to the main...

Page 88: ...if CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT 0 io_cfg isDQ32Bit CyFalse io_cfg lppMode CY_U3P_IO_MATRIX_LPP_UART_ONLY else io_cfg isDQ32Bit CyTrue io_cfg lppMode CY_U3P_IO_MATRIX_LPP_DEFAULT endif No GP...

Page 89: ...ack CY_FX_SLFIFO_THREAD_STACK App Thread stack size CY_FX_SLFIFO_THREAD_PRIORITY App Thread priority CY_FX_SLFIFO_THREAD_PRIORITY App Thread pre emption threshold CYU3P_NO_TIME_SLICE No time slice for...

Page 90: ...voking the UART init function Initialize the UART for printing debug messages apiRetStatus CyU3PUartInit The next step is to configure the UART The UART data structure is first filled in and this is p...

Page 91: ...se apiRetStatus CyU3PPibInit CyTrue pibClock The slave FIFO descriptors are loaded into the GPIF II registers and the state machine is started Load the GPIF configuration for Slave FIFO sync mode apiR...

Page 92: ...USB_SET_HS_DEVICE_DESCR NULL uint8_t CyFxUSB20DeviceDscr The code snippet above is for setting the Device Descriptor The other descriptors set in the example are Device Qualifier Other Speed Configura...

Page 93: ...piRetStatus Consumer endpoint configuration apiRetStatus CyU3PSetEpConfig CY_FX_EP_CONSUMER epCfg if apiRetStatus CY_U3P_SUCCESS CyU3PDebugPrint 4 CyU3PSetEpConfig failed Error code d n apiRetStatus C...

Page 94: ...ve CyFxSlFifoApplnStop Start the loop back function CyFxSlFifoApplnStart break case CY_U3P_USB_EVENT_RESET case CY_U3P_USB_EVENT_DISCONNECT Stop the loop back function if glIsApplnActive CyFxSlFifoApp...

Page 95: ...cb CyFxSlFifoPtoUDmaCallback apiRetStatus CyU3PDmaChannelCreate glChHandleSlFifoPtoU CY_U3P_DMA_TYPE_MANUAL dmaCfg if apiRetStatus CY_U3P_SUCCESS CyU3PDebugPrint 4 CyU3PDmaChannelCreate failed Error...

Page 96: ...tion is received upon reception of every buffer The buffer will not be sent out unless it is explicitly committed The call shall fail if there is a bus reset usb disconnect or if there is any applica...

Page 97: ...y buffer The buffer will not be sent out unless it is explicitly committed The call shall fail if there is a bus reset usb disconnect or if there is any application error status CyU3PDmaChannelCommitB...

Page 98: ...98 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Application Structure...

Page 99: ...ations and modes register I2S_STATUS 32 0xE0000004 Status register I2S_INTR 32 0xE0000008 Interrupt request status register I2S_INTR_MASK 32 0xE000000C Interrupt mask register I2S_EGRESS_DATA_LEFT 32...

Page 100: ...RW 1 0 8 bit 1 16 bit 2 18 bit 3 24 bit 4 32 bit 5 7 Reserved 12 11 MODE R RW 0 0 3 I2S Mode 1 Left Justified Mode 2 Right Justified Mode 30 TX_CLEAR R RW 0 0 Do nothing 1 Clear transmit FIFO Use onl...

Page 101: ...o EGRESS_DATA_LEFT register Only relevant when DMA_MODE 0 Non sticky 3 TXR_DONE W R 0 Indicates no more data is available for transmis sion on right channel Non sticky If DMA_MODE 0 this is defined as...

Page 102: ...nd must be polled before changing any configuration values Bits Field Name HW Access SW Access Default Value Description 0 TXL_DONE RW1S RW1C 0 Set by hardware when I2S_STATUS TXL_DONE assert cleared...

Page 103: ...1 TXL_SPACE R RW 0 Enable reporting of I2S_INTR TXL_SPACE to CPU 2 TXL_HALF R RW 0 Enable reporting of I2S_INTR TXL_HALF to CPU 3 TXR_DONE R RW 0 Enable reporting of I2S_INTR TXR_DONE to CPU 4 TXR_SPA...

Page 104: ...that can be used by the CPU to verify that the I2S block is functioning Bits Field Name HW Access SW Access Default Value Description 31 0 COUNTER RW R 0 Counter increments by one for every sample wri...

Page 105: ...reset Name Width bits Address Description I2C_CONFIG 32 0xE0000400 Configuration and modes register I2C_STATUS 32 0xE0000404 Status register I2C_INTR 32 0xE0000408 Interrupt status register I2C_INTR_...

Page 106: ...when ENABLE 1 Once TX_CLEAR is set firmware must wait for TX_DONE before clearing it 31 ENABLE R RW 0 Enable block here but only after all other con figuration is set Do not set this bit to 1 while ch...

Page 107: ...d Sticky 8 ERROR RW1S RW1C 0 An internal error has occurred with cause ERROR_CODE Must be cleared by software Sticky 27 24 ERROR_CODE W R 0xF Error code only relevant when ERROR 1 This only logs the F...

Page 108: ...ftware 3 TX_DONE RW1S RW1C 0 Set when I2C_STATUS TX_DONE asserts cleared by software 4 TX_SPACE RW1S RW1C 0 Set when I2C_STATUS TX_SPACE asserts cleared by software 5 TX_HALF RW1S RW1C 0 Set when I2C_...

Page 109: ...ny device specific address bytes that precede the actual data transfer The length of the preamble phase in bytes depends on the I2 C slave and direction of data transfer The slave protocol may also re...

Page 110: ...DATA1 register Bits Field Name HW Access SW Access Default Value Description 0 RPT_ENABLE R RW 0 1 Turns on preamble repeat feature The sequence from IDLE to preamble_complete repeats in a program mab...

Page 111: ...ART_FIRST R RW 1 1 Send START before the first byte of preamble 0 Do nothing before the first byte of pre amble 28 READ R RW 0 0 The data phase is a write operation 1 The data phase is a read operatio...

Page 112: ...s transferred in the data phase so far Does not include preamble bytes Useful for determining when NACK hap pened during data transmission Bits Field Name HW Access SW Access Default Value Description...

Page 113: ...0818 Socket selection register UART_RX_BYTE_COUNT 32 0xE000081C Receive byte count register UART_TX_BYTE_COUNT 32 0xE0000820 Transmit byte count register UART_ID 32 0xE0000BF0 Block ID register UART_P...

Page 114: ...tting byte to complete including the stop bit and then transmit 0s indefinitely until this bit is cleared Do not transmit other bytes or discard any data while BREAK is being transmitted 19 16 RX_POLL...

Page 115: ...fined as TX FIFO empty and shift register empty If DMA_MODE 1 this is defined as BYTE_COUNT 0 and shift register empty 4 TX_SPACE W R 1 Indicates space is available in the TX FIFO This bit is updated...

Page 116: ...ware when UART_STATUS RX_DATA asserts cleared by software 2 RX_HALF RW1S RW1C 0 Set by hardware when UART_STATUS RX_HALF asserts cleared by software 3 TX_DONE RW1S RW1C 0 Set by hardware when UART_STA...

Page 117: ...TA R RW 0 1 Enables reporting of UART_INTR RX_DATA to the CPU 2 RX_HALF R RW 0 1 Enables reporting of UART_INTR RX_HALF to the CPU 3 TX_DONE R RW 0 1 Enables reporting of UART_INTR TX_DONE to the CPU...

Page 118: ...when the count reaches zero 9 1 3 10 UART_ID register The block ID register is a read only register that allows the CPU to identify whether the UART block is powered on Bits Field Name HW Access SW A...

Page 119: ...R RW 0 Active LOW reset signal for all logic in the block After setting this bit to 1 firmware polls and waits for the active bit to assert Assert this bit 0 for at least 10 s for effective block res...

Page 120: ...asserts high at the end of the transfer 11 SSN is governed by CPHA 10 CPOL R RW 0 0 SCK idles low 1 SCK idles high 11 CPHA R RW 0 Transaction start mode 13 12 LEAD R RW 1 SSN SCK lead time Indicates t...

Page 121: ...bytes in socket have been received 1 RX_DATA W R 0 Indicates data is available in the RX FIFO Non sticky Only relevant when DMA_MODE 0 This bit is updated immediately after reads from INGRESS_DATA re...

Page 122: ...RX_DONE RW1S RW1C 0 Set when SPI_STATUS RX_DONE asserts cleared by software 1 RX_DATA RW1S RW1C 0 Set when SPI_STATUS RX_DATA asserts cleared by software 2 RX_HALF RW1S RW1C 0 Set when SPI_STATUS RX_H...

Page 123: ...e 5 TX_HALF R RW 0 1 Enable the reporting of SPI_INTR TX_HALF interrupt to CPU 6 ERROR R RW 0 1 Enable the reporting of SPI_INTR ERROR interrupt to CPU Bits Field Name HW Access SW Access Default Valu...

Page 124: ...the block is powered on Bits Field Name HW Access SW Access Default Value Description 7 0 EGRESS_SOCKET R RW 0 Socket number for egress data 0 7 Supported Should be set to 4 15 8 INGRESS_SOCKET R RW...

Page 125: ...The following table lists key registers of the simple GPIO interface Table 9 1 Simple GPIO Registers Bits Field Name HW Access SW Access Default Value Description 0 ACTIVE W R 0 Indicates whether the...

Page 126: ...is tristated 1 Output driver is active weak strong is determined in IO Matrix 5 DRIVE_HI_EN R RW 0 Output driver enable when OUT_VALUE 1 0 Output driver is tristated 1 Output driver is active weak str...

Page 127: ...GPIO 9 3 Complex GPIO PIN Registers The following table lists key registers of the complex GPIO interface Table 9 2 Complex GPIO Registers The following table lists the pins registers for complex GPI...

Page 128: ...0 32 PIN_PERIOD Period length for revolving counter timer GPIO_TIMER 0xE000100C GPIO_ID MOD 8 0x10 32 PIN_THRESHOLD Threshold for measurement register Bits Name HW SW Default Description 0 OUT_VALUE R...

Page 129: ..._VALUE is low 5 Interrupt when IN_VALUE is high 6 Interrupt on TIMER THRESHOLD 7 Interrupt on TIMER 0 27 INTR RW1S RW1C 0 Registers edge triggered interrupt condition Only relevant when INTRMODE 1 2 3...

Page 130: ...e if any is set in GCTL_GPIO_COMPLEX This register is valid only for complex GPIO Bits Name HW SW Default Description 31 0 TIMER RW RW 0 32 bit timer counter value Use MODE SAMPLE_NOW to sample the ti...

Page 131: ...es in the range 0x80 FF expose a bank of 128 16 bit registers Some of these regis ters are used to implement the mechanisms mentioned below and others control configuration sta tus and behavior of the...

Page 132: ...NIT P Port reset and power control 0x08 16 PP_CONFIG P Port Configuration Register 0x1C 16 PP_INTR_MASK P Port Interrupt Mask Register 0x20 16 PP_DRQR5_MASK P Port DRQ R5 Mask Register 0x24 32 PP_SOCK...

Page 133: ...L_CONTROL 3 WAKEUP_PWR RW R 0 Indicates system woke up from standby mode see architecture spec for details If firmware does not clear this bit it will stay 1 even through suspend sequences This bit is...

Page 134: ...cure This bit is mirrored directly by HW in PIB_CONFIG 7 DRQMODE R RW 0 DMA signaling mode See DMA section for more information 0 Pulse mode DRQ will de assert when DACK de asserts and will remain de...

Page 135: ...R R RW 0 1 Forward EVENT onto INT line 7 GPIF_ERR R RW 0 1 Forward EVENT onto INT line 11 DMA_WMARK_EV R RW 0 1 Forward EVENT onto INT line 12 DMA_READY_EV R RW 0 1 Forward EVENT onto INT line 13 RD_M...

Page 136: ...no transfer is ongoing ignore disable 1 Enable data transfer 9 DMA_DIRECTION R RW 0 0 Read Transfer from Bay Egress direc tion 1 Write Transfer to Bay Ingress direction 10 LONG_TRANSFER R RW 0 0 Short...

Page 137: ...ister indicates all types of events that can cause INTR or DRQ to assert Bits Name HW SW Default Description 15 0 DMA_SIZE RW RW 0 Size of DMA transfer Number of bytes available for read write when re...

Page 138: ...QR5_MASK It is possible to combine DMA_READY or DMA_WMARK with a handshake DACK signal from AP if required This is done using a programmable GPIF state machine For the rest of this document use of DAC...

Page 139: ...s with offset latencies in the signaling interface 4 PP_DMA_XFER LONG_TRANSFER This config bit indicates if long multi buffer transfers are enabled This bit is set by Application Processor as part of...

Page 140: ...een activated to indicate data transfer can start This can occur before during or after the DMA_SIZE read mentioned above 7 DMA_SIZE bytes are transferred in an integral number of full bursts The numb...

Page 141: ...XFER Note that in that case it is not possible to transfer an odd number of bytes Application Processor GPMC port Benicia P port AP gets interrrupted by INTR AP reads PP_SOCK_STAT and determins socket...

Page 142: ...shortly after all data for the current buf fer is exchanged However DMA_READY and DMA_ENABLE remain asserted until the last burst if fully completed or the transfer is aborted A transfer can be abort...

Page 143: ...ID 1 For write transfers all signals de assert shortly after the write of DMA_SIZE 0 10 4 5 Long Transfer Integral Number of Buffers A long transfer is coordinated between AP and Benicia CPU using a h...

Page 144: ...h data is transferred the AP must terminate the transfer by writing DMA_ENABLE 0 10 4 6 Long Transfer Aborted by AP A long transfer can be aborted by AP by writing DMA_ENABLE 0 at any time and follow...

Page 145: ...ffer The following should be noted Before transferring the last buffer the AP adjusts DMA_SIZE AP must assure that DMA_READY 1 or DMA_WMARK 1 before writing to DMA_SIZE This can be done using the sign...

Page 146: ...he figure illustrates DRQ signaling on P port interface for a long transfer In this figure DMA_WMARK is mapped to DRQ signal Note that DRQ is programmed active low in this exam ple The buffer switchin...

Page 147: ...Burst of 16 Read on ADMux Interface A 0 7 DQ 0 31 ADV CE WE tAVWE tS Valid Address tS D1 tH tS tH tDH tDS tCLKH tCLKL tCLK CLK D0 RDY High Z tKW tWZ tKW Note 1 2 cycle latency is shown 2 RDY active h...

Page 148: ...148 FX3 Programmers Manual Doc 001 64707 Rev C FX3 P Port Register Access...

Page 149: ...B Micro chip 6 64KB 128K ATMEL 5 32KB 4 16KB 3 8KB 2 4KB Note Options 1 and 0 are reserved for future usage Unpredicted result will occurred when boot ing in these modes Bit5 4 I2C speed on I2C Boot 0...

Page 150: ...ore sections dLength N 2 0x00000000 Last record termination section dAddress N 2 Should contain valid Program Entry Normally it should be the Start up code i e the RESET Vector Note if bImageCTL bit0...

Page 151: ...r C C Developer is provided as part of the FX3 SDK This IDE comprises of the base Eclipse platform 3 5 2 and the CPP feature 1 2 2 A couple of plugins required for develop ment are bundled with the ID...

Page 152: ...ate a new application project using FX3 SDK 12 2 2 1 Importing Eclipse Projects Eclipse projects are provided with each FX3 firmware example These have to be imported into eclipse before they can be u...

Page 153: ...FX3 Programmers Manual Doc 001 64707 Rev C 153 FX3 Development Tools 2 Select General Existing projects into Workspace...

Page 154: ...154 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools 3 Select the root directory where the eclipse projects are available This will be the directory where the FX3 SDK is installed...

Page 155: ...inish At the end of this step all the projects for the FX3 firmware examples have been imported into the eclipse workbench 12 2 2 2 Building Projects After the projects have been imported they have to...

Page 156: ...cally built after an import The build console displays the build messages 12 2 2 3 Executing and Debugging 1 The GNU debugger gdb connects to the target FX3 hardware using the J Link GDB server from S...

Page 157: ...nce the JTAG is connected and the GDB server is run the ARM9 core will appear con nected on the GDB server window as shown below The Init regs on start will be checked by default Please ensure to un c...

Page 158: ...158 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools 2 The first step is to create a debug configuration for the project Select Debug Configurations...

Page 159: ...ew configuration A new configuration window opens up 4 The debug settings must be modified The first setting that needs to change is in the Debugger tab The default setting uses the native gdb as the...

Page 160: ...PC s tcp port 2331 target remote localhost 2331 monitor speed 1000 monitor endian little set endian little monitor reset Set the processor to SVC mode monitor reg cpsr 0xd3 Disable all interrupts moni...

Page 161: ...nput is 19 2 MHz Value 0x00080015 Clock input is 26 0 MHz Value 0x00080010 Clock input is 38 4 MHz Value 0x00080115 Clock input is 52 0 MHz Value 0x00080110 monitor memU32 0xE0052000 0x00080015 Add a...

Page 162: ...mers Manual Doc 001 64707 Rev C FX3 Development Tools 6 Once the debug is launched the executable is loaded and the debug screen is displayed The execution is halted at the instruction specified in th...

Page 163: ...163 FX3 Development Tools 7 If the execution is resumed it will stop at a breakpoint if one has been set 12 2 2 4 Creating New Eclipse Projects New projects can be created in eclipse The following ste...

Page 164: ...ment Tools 1 Select File New C project 2 Select ARM Cross Target Application Empty project Select Arm Windows GCC Sourcery G Lite Select the folder where the project must be created This must be the f...

Page 165: ...FX3 Programmers Manual Doc 001 64707 Rev C 165 FX3 Development Tools Click next...

Page 166: ...166 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools 3 Click on Advanced Settings to get the settings window Here we are updating the debug configu ration...

Page 167: ...FX3 Programmers Manual Doc 001 64707 Rev C 167 FX3 Development Tools 4 Click on C C Build Settings The first setting is the target processor Select arm926ej s as the processor Click on Apply...

Page 168: ...168 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools 5 The next settings are for debug Select the default debug level g and the dwarf 2 debug format Click on Apply...

Page 169: ...FX3 Programmers Manual Doc 001 64707 Rev C 169 FX3 Development Tools Select the default debug level none for release configuration Click on Apply...

Page 170: ...170 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools 6 The next settings are for Additional tools Un check the Create Flash Image box Click on Apply...

Page 171: ...oc 001 64707 Rev C 171 FX3 Development Tools 7 The next settings are for the Assembler Click on ARM Sourcery Windows GCC Assembler Click on Directories and add FX3_INSTALL_PATH firmware u3p_firmware i...

Page 172: ...Programmers Manual Doc 001 64707 Rev C FX3 Development Tools 8 The next settings are for the Compiler Click on ARM Sourcery Windows GCC C Compiler Click on Preprocessor and add __CYU3P_TX__ 1 Click o...

Page 173: ...s Manual Doc 001 64707 Rev C 173 FX3 Development Tools 9 The next settings are also for the Compiler Click on ARM Sourcery Windows GCC C Compiler Click on Directories and add the relevant directories...

Page 174: ...174 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools 10 The next settings are also for the Compiler Select optimization level None O0 for Debug mode Click on Apply...

Page 175: ...FX3 Programmers Manual Doc 001 64707 Rev C 175 FX3 Development Tools Select optimization level Optimize size Os for Release mode Click on Apply...

Page 176: ...Doc 001 64707 Rev C FX3 Development Tools 11 The next settings are for the Linker Click on ARM Sourcery Windows GCC C Linker In the Command Line Pattern box move the INPUTS field to immediately after...

Page 177: ...also for the Linker Click on ARM Sourcery Windows GCC C Linker Click on Miscellaneous and add the libraries to be linked The actual command is Wl d Wl no wchar size warning Wl entry CyU3PFirmwareEntr...

Page 178: ...178 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools Click on Apply...

Page 179: ...g Process The debugger can be attached to an already running process This is required when the executable has been downloaded to the FX3 by means other than JTAG USB I2C SPI boot The following steps d...

Page 180: ...180 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools d Start the GDB server...

Page 181: ...anual Doc 001 64707 Rev C 181 FX3 Development Tools 2 Open the eclipse project which was used to build the currently running process Create a new debug configuration for this project Select Zylin Embe...

Page 182: ...182 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools 3 In the Debugger tab change the GDB Debugger to arm none eabi gdb exe and leave the GDB command file blank...

Page 183: ...FX3 Programmers Manual Doc 001 64707 Rev C 183 FX3 Development Tools 4 In the Commands tab only a single Load command is specified target remote localhost 2331 Click on Debug...

Page 184: ...a unix linux machine or on windows which has a Cygwin environment Invoking the make file in the firmware directory will build all the example projects Indi vidual makefiles in the example project dire...

Page 185: ...FX3 Programmers Manual Doc 001 64707 Rev C 185 FX3 Development Tools...

Page 186: ...186 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools...

Page 187: ...FX3 Programmers Manual Doc 001 64707 Rev C 187 FX3 Development Tools...

Page 188: ...188 FX3 Programmers Manual Doc 001 64707 Rev C FX3 Development Tools...

Page 189: ...diagnostic applications Kindly refer to the CyUSB pdf in the Cypress SuperSpeed USBSuite installation for more details 13 1 2 CYAPI Programmer s reference CyAPI lib provides a simple powerful C progr...

Page 190: ...1 4 Cy Control Center USB ControlCenter is a C Sharp application that is used to communicate with Cypress USB devices that are served by CyUSB3 sys device driver Kindly refer to the CyControlCenter p...

Page 191: ...configuration in the form of a header file that can be readily integrated with the FX3 firmware application using the FX3 API library Please refer to the GPIF II Designer User Guide for more details o...

Page 192: ...192 FX3 Programmers Manual Doc 001 64707 Rev C GPIF II Designer...

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