Cypress CYW43353, Manual

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Document No. 002-14949 Rev. *E Page 95 of 113
PRELIMINARY
CYW43353
18. Interface Timing and AC Characteristics
18.1 SDIO/gSPI Timing
18.1.1 SDIO Default Mode Timing
SDIO default mode timing is shown by the combination of Figure 32 and Table 44 .
Figure 32. SDIO Bus Timing (Default Mode)
Table 44. SDIO Bus Timing
1
Parameters (Default Mode)
1. Timing is based on CL

40pF load on CMD and Data.
Parameter Symbol Minimum Typical Maximum Unit
SDIO CLK (All values are referred to minimum VIH and maximum VIL
2
)
2. Min. (Vih) = 0.7 × VDDIO and max (Vil) = 0.2 × VDDIO.
Frequency – Data Transfer mode fPP 0 – 25 MHz
Frequency – Identification mode fOD 0 – 400 kHz
Clock low time tWL 10 – – ns
Clock high time tWH 10 – – ns
Clock rise time tTLH – – 10 ns
Clock fall time tTHL – – 10 ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time tISU 5 – – ns
Input hold time tIH 5 – – ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer mode tODLY 0 – 14 ns
Output delay time – Identification mode tODLY 0 – 50 ns
t
WL
t
WH
f
PP
t
THL
t
ISU
t
TLH
t
IH
t
ODLY
(max)
t
ODLY
(min)
Input
Output
SDIO_CLK