Document No. 002-14949 Rev. *E
Page 37 of 113
PRELIMINARY
CYW43353
Note:
The time periods specified in
and
are defined by the transmitter speed. The receiver specifications must
match transmitter performance.
Figure 14. I
2
S Transmitter Timing
1.
The system clock period T must be greater than T
tr
and T
r
because both the transmitter and receiver have to be able to handle the data transfer rate.
2. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, t
HC
and t
LC
are specified with respect to T.
3. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal.
So long as the minimum periods are greater than 0.35T
r
, any clock that meets the requirements can be used.
4. Because the delay (t
dtr
) and the maximum transmitter speed (defined by T
tr
) are related, a fast transmitter driven by a slow clock edge
can result in t
dtr
not exceeding t
RC
which means t
htr
becomes zero or negative. Therefore, the transmitter has to guarantee that t
htr
is
greater than or equal to zero, so long as the clock rise-time t
RC
is not more than t
RCmax
, where t
RCmax
is not less than 0.15T
tr
.
5. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always
giving the receiver sufficient setup time.
6. The data setup and hold time must not be less than the specified receiver setup and hold time.
SD
and
WS
SCK
V
L
=
0.8V
t
LC
> 0.35T
t
RC
*
t
HC
> 0.35T
T
V
H
=
2.0V
t
htr
> 0
t
otr
< 0.8T
T
=
Clock
period
T
tr
=
Minimum
allowed
clock
period
for
transmitter
T
=
T
tr
*
t
RC
is
only
relevant
for
transmitters
in
slave
mode.
