248
CY8C28xxx PSoC Programmable System-on-Chip TRM, Document No. 001-52594 Rev. *G
SADC_TSCR1
1,72h
13.3.28
SADC_TSCR1
SAR ADC Trigger Source Control Register 1
This register controls the selection of digital blocks for high and low channel comparison.
The 10-bit SAR ADC controller only exists in the CY8C28x03, CY8C28x13, CY8C28x33, CY8C28x43, and CY8C28x45
PSoC devices. This register is not used for the CY8C28x23 and CY8C28x52 devices. For additional information, refer to the
“Register Definitions” on page 541
in the 10-Bit SAR ADC Controller chapter.
6:4
TS_CMPH_SEL[2:0]
Selects a digital block's DR0 register to compare against SADC_TSCMPH. When the comparison is
equal an ADC sample is triggered.
000b DBB00
001b
DBB01
010b
DCB02
011b
DCB03
100b
DBB10
101b
DBB11
110b
DCB12
111b
DCB13
2:0
TS_CMPL_SEL[2:0]
Selects a digital block's DR0 register to compare against SADC_TSCMPL. When the comparison is
equal an ADC sample is triggered.
000b DBB00
001b
DBB01
010b
DCB02
011b
DCB03
100b
DBB10
101b
DBB11
110b
DCB12
111b
DCB13
Individual Register Names and Addresses:
1,72h
SADC_TSCR1: 1,72h
7
6
5
4
3
2
1
0
Access : POR
RW : 000
RW : 000
Bit Name
TS_CMPH_SEL[2:0]
TS_CMPL_SEL[2:0]
Bit
Name
Description
Summary of Contents for CY8C28 series
Page 65: ...64 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G RAM Paging ...
Page 125: ...124 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G ...
Page 311: ...310 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G IDAC_CR0 1 FDh ...
Page 317: ...316 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G ...
Page 393: ...392 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G ...
Page 477: ...476 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G Digital Clocks ...
Page 561: ...560 CY8C28xxx PSoC Programmable System on Chip TRM Document No 001 52594 Rev G ...