Kit Operation
CY3677 Evaluation Kit User Guide, Doc. No. 002-12185 Rev. *D
14
3.2 Functional Description
The differential clock outputs (J7, J8) and single-ended output (J10) are driven out on to SMA connectors. The EVK is
populated with 50-
resistors (R30 and R31) for output termination. The termination options of the differential outputs on the
evaluation board are listed in the
Hardware
chapter. These termination circuits are designed to terminate the output clocks in
LVPECL, LVDS, HCSL, LVPECL2, and CML signal types by populating, or by not populating the J5 jumper shunt. The single-
ended (LVCMOS) clock does not need any on-board termination settings.
Figure 3-2
illustrates the top view and bottom view of the CY3677 EVK.
Figure 3-2. CY3677 EVK (Top View, Bottom View)
CY3677 EVK Top View
CY3677 EVK Bottom View
3.3 CY3677 EVK USB Connection
The CY29430 clock device on the kit is loaded with a default configuration. To view and evaluate other configurations on an
oscilloscope (or other standard instruments), the clock device must be programmed with the desired configuration. The
ClockWizard 2.1 application is required for programming any configuration. Therefore, the kit should be connected (see
Figure 3-3
) to a PC through a USB port for programming.
Figure 3-3. Kit Connected through USB