CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Document #: 38-05354 Rev. *D
Page 7 of 27
Functional Overview
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
synchronous-pipelined Burst NoBL SRAMs designed specifi-
cally to eliminate wait states during Write/Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise
(t
CO
) is 2.6 ns (250-MHz device).
Accesses can be initiated by asserting all three Chip Enables
(CE
1
, CE
2
, CE
3
) active at the rising edge of the clock. If Clock
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW
[x]
can be used to
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and (4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the input of the output register. At the rising edge
of the next clock the requested data is allowed to propagate
through the output register and onto the data bus within 2.6 ns
(200-MHz device) provided OE is active LOW. After the first
clock of the read access the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. During the
second clock, a subsequent operation (Read/Write/Deselect)
can be initiated. Deselecting the device is also pipelined.
Therefore, when the SRAM is deselected at clock rise by one
of the chip enable signals, its output will three-state following
the next clock rise.
Burst Read Accesses
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 have
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four Reads without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load a new address into the SRAM, as described in
the Single Read Access section above. The sequence of the
burst counter is determined by the MODE input signal. A LOW
input on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and
A1 in the burst sequence, and will wrap-around when incre-
mented sufficiently. A HIGH input on ADV/LD will increment
the internal burst counter regardless of the state of chip
enables inputs or WE. WE is latched at the beginning of a burst
cycle. Therefore, the type of access (Read or Write) is
maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, and (3) the write signal WE
is asserted LOW. The address presented to the address inputs
is loaded into the Address Register. The write signals are
latched into the Control Logic block.
On the subsequent clock rise the data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ
and DQP
(DQ
a,b,c,d,e,f,g,h
/DQP
a,b,c,d,e,f,g,h
for CY7C1464AV25,
DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1460AV25 and DQ
a,b
/DQP
a,b
for CY7C1462AV25). In addition, the address for the subse-
quent access (Read/Write/Deselect) is latched into the
Address Register (provided the appropriate control signals are
asserted).
On the next clock rise the data presented to DQ
and DQP
(DQ
a,b,c,d,e,f,g,h
/DQP
a,b,c,d,e,f,g,h
for CY7C1464AV25,
DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1460AV25 and DQ
a,b
/DQP
a,b
for CY7C1462AV25) (or a subset for byte write operations, see
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the Write operation is controlled by BW
(BW
a,b,c,d,e,f,g,h
for CY7C1464AV25, BW
a,b,c,d
for
CY7C1460AV25 and BW
a,b
for CY7C1462AV25) signals. The
CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 provides
byte write capability that is described in the Write Cycle
Description table. Asserting the Write Enable input (WE) with
the selected Byte Write Select (BW) input will selectively write
to only the desired bytes. Bytes not selected during a byte
write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations. Byte write capability has been included in
order to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple byte write operations.
Because the CY7C1460AV25/CY7C1462AV25/CY7C1464AV25
are common I/O devices, data should not be driven into the
device while the outputs are active. The Output Enable (OE)
can be deasserted HIGH before presenting data to the DQ
and
DQP (DQ
a,b,c,d,e,f,g,h
/DQP
a,b,c,d,e,f,g,h
for CY7C1464AV25,
DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1460AV25 and DQ
a,b
/DQP
a,b
for CY7C1462AV25) inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ
and DQP
(DQ
a,b,c,d,e,f,g,h
/DQP
a,b,c,d,e,f,g,h
for CY7C1464AV25,
DQ
a,b,c,d
/DQP
a,b,c,d
for CY7C1460AV25 and DQ
a,b
/DQP
a,b
for CY7C1462AV25) are automatically three-stated during the
data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four WRITE opera-
tions without reasserting the address inputs. ADV/LD must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
driven HIGH on the subsequent clock rise, the chip enables
(CE
1
, CE
2
, and CE
3
) and WE inputs are ignored and the burst
counter is incremented. The correct BW (BW
a,b,c,d,e,f,g,h
for
[+] Feedback
