Cypress Semiconductor NoBL CY7C1460AV25 Manual Download Page 5

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CY7C1460AV25
CY7C1462AV25
CY7C1464AV25

Document #: 38-05354 Rev. *D

Page 5 of 27

Pin Configurations

(continued)

DQg

DQc

DQPg

DQh

DQd

DQPd

DQPc

DQc

DQh

DQPh

DQd

DQb

DQf

DQPf

DQa

DQe

DQPa

DQPb

DQf

DQa

DQPe

DQe

NC/144M

NC/72M

NC/288M

NC/1G

NC/576M

BWS

TMS

TDI

TDO

TCK

MODE

CEN

CLK

ADV/LD

DDQ

209-ball FBGA (14 x 22 x 1.76 mm) Pinout

CY7C1464AV25 (512K x 72)

Pin Definitions

Pin Name

I/O Type

Pin Description

A0
A1

Input-

Synchronous

Address Inputs used to select one of the address locations

. Sampled at the rising edge of

the CLK.

Input-

Synchronous

Byte Write Select Inputs, active LOW

. Qualified with WE to conduct writes to the SRAM.

Sampled on the rising edge of CLK. BW

controls DQ

and DQP

, BW

controls DQ

and DQP

controls DQ

and DQP

, BW

controls DQ

and DQP

, BW

controls DQ

and DQP

controls DQ

and DQP

controls DQ

and DQP

controls DQ

and DQP

Input-

Synchronous

Write Enable Input, active LOW

. Sampled on the rising edge of CLK if CEN is active LOW. This

signal must be asserted LOW to initiate a write sequence.

ADV/LD

Input-

Synchronous

Advance/Load Input used to advance the on-chip address counter or load a new address

When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.

CLK

Input-
Clock

Clock Input

. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.

CLK is only recognized if CEN is active LOW.

[+] Feedback

Summary of Contents for NoBL CY7C1460AV25

Page 1: ...ogic required to enable consecutive Read Write operations with data being trans ferred on every clock cycle This feature dramatically improves the throughput of data in systems that require frequent Write Read transitions The CY7C1460AV25 CY7C1462AV25 CY7C1464AV25 are pin compatible and functionally equivalent to ZBT devices All synchronous inputs pass through input registers controlled by the ris...

Page 2: ... A0 A1 D1 D0 Q1 Q0 A0 A1 C ADV LD ADV LD E INPUT REGISTER 1 S E N S E A M P S O U T P U T R E G I S T E R S E CLK CEN WRITE DRIVERS ZZ Sleep Control Logic Block Diagram CY7C1462AV25 2M x 18 A0 A1 A C MODE CE1 CE2 CE3 OE READ LOGIC DQs DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh D A T A S T E E R I N G O U T P U T B U F F E R S MEMORY ARRAY E E INPUT REGISTER0 ADDRESS REGISTER 0 WRITE ADDRESS REGISTER ...

Page 3: ...C1460AV25 100 pin TQFP Pinout A A A A A 1 A 0 V SS V DD A A A A A A A NC NC VDDQ VSS NC DQP DQa DQa VSS VDDQ DQa DQa VSS NC VDD DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VDD VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC A A CE 1 CE 2 NC NC BWb BWa CE 3 V DD V SS CLK WE CEN OE A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ...

Page 4: ...b VDD NC VDD DQa VDD VDDQ DQa VDDQ VDD VDD VDDQ VDD VDDQ DQa VDDQ A A VSS A A A DQb DQb DQb ZZ DQa DQa DQPa DQa A VDDQ A 2 3 4 5 6 7 1 A B C D E F G H J K L M N P R TDO NC 576M NC 1G NC NC DQPb NC DQb A CE1 CE3 BWb CEN A CE2 NC DQb DQb MODE NC DQb DQb NC NC NC NC 72M VDDQ BWa CLK WE VSS VSS VSS VSS VDDQ VSS VDD VSS VSS VSS NC VSS VSS VSS VSS VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ A A VDD VSS VDD VSS VSS...

Page 5: ...inout CY7C1464AV25 512K x 72 Pin Definitions Pin Name I O Type Pin Description A0 A1 A Input Synchronous Address Inputs used to select one of the address locations Sampled at the rising edge of the CLK BWa BWb BWc BWd BWe BWf BWg BWh Input Synchronous Byte Write Select Inputs active LOW Qualified with WE to conduct writes to the SRAM Sampled on the rising edge of CLK BWa controls DQa and DQPa BWb ...

Page 6: ...erging from a deselected state and when the device is deselected regardless of the state of OE DQPa DQPb DQPc DQPd DQPe DQPf DQPg DQPh I O Synchronous Bidirectional Data Parity I O lines Functionally these signals are identical to DQ 31 0 During write sequences DQPa is controlled by BWa DQPb is controlled by BWb DQPc is controlled by BWc and DQPd is controlled by BWd DQPe is controlled by BWe DQPf...

Page 7: ... the burst sequence and will wrap around when incre mented sufficiently A HIGH input on ADV LD will increment the internal burst counter regardless of the state of chip enables inputs or WE WE is latched at the beginning of a burst cycle Therefore the type of access Read or Write is maintained throughout the burst sequence Single Write Accesses Write access are initiated when the following conditi...

Page 8: ...his parameter is sampled 0 ns Truth Table 1 2 3 4 5 6 7 Operation Address Used CE ZZ ADV LD WE BWx OE CEN CLK DQ Deselect Cycle None H L L X X X L L H Tri State Continue Deselect Cycle None X L H X X X L L H Tri State Read Cycle Begin Burst External L L L H X L L L H Data Out Q Read Cycle Continue Burst Next X L H X X L L L H Data Out Q NOP Dummy Read Begin Burst External L L L H X H L L H Tri Sta...

Page 9: ...H H Write Bytes d a L L H H L Write Bytes d b L L H L H Write Bytes d b a L L H L L Write Bytes d c L L L H H Write Bytes d c a L L L H L Write Bytes d c b L L L L H Write All Bytes L L L L L Function CY7C1462AV25 WE BWb BWa Read H X X Write No Bytes Written L H H Write Byte a DQa and DQPa L H L Write Byte b DQb and DQPb L L H Write Both Bytes L L L Function CY7C1464AV25 WE BWx Read H X Write No B...

Page 10: ...e unconnected if the TAP is unused in an application TDI is connected to the most signif icant bit MSB of any register See Tap Controller Block Diagram Test Data Out TDO The TDO output ball is used to serially clock data out from the registers The output is active depending upon the current state of the TAP state machine The output changes on the falling edge of TCK TDO is connected to the least s...

Page 11: ...up or whenever the TAP controller is given a test logic reset state SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift DR state The SAMPLE Z command puts the output bus into a High Z state until the next command is given during the Update IR state SAMPLE PRELOAD SAMPLE PRELOAD is a 1149 1 mandatory ...

Page 12: ...he TAP controller is in the Test Logic Reset state Reserved These instructions are not implemented but are reserved for future use Do not use these instructions TAP Timing t TL Test Clock TCK 1 2 3 4 5 6 Test Mode Select TMS tTH Test Data Out TDO tCYC Test Data In TDI tTMSH tTMSS tTDIH tTDIS tTDOX tTDOV DON T CARE UNDEFINED TAP AC Switching Characteristics Over the Operating Range 9 10 Parameter D...

Page 13: ...V VOH2 Output HIGH Voltage IOH 100 µA VDDQ 2 5V 2 1 V VDDQ 1 8V 1 6 V VOL1 Output LOW Voltage IOL 1 0 mA VDDQ 2 5V 0 4 V VOL2 Output LOW Voltage IOL 100 µA VDDQ 2 5V 0 2 V VDDQ 1 8V 0 2 V VIH Input HIGH Voltage VDDQ 2 5V 1 7 VDD 0 3 V VDDQ 1 8V 1 26 VDD 0 3 V VIL Input LOW Voltage VDDQ 2 5V 0 3 0 7 V VDDQ 1 8V 0 3 0 36 V IX Input Load Current GND VI VDDQ 5 5 µA Identification Register Definitions ...

Page 14: ...ith the vendor ID code and places the register between TDI and TDO This operation does not affect SRAM operations SAMPLE Z 010 Captures I O ring contents Places the boundary scan register between TDI and TDO Forces all SRAM output drivers to a High Z state RESERVED 011 Do Not Use This instruction is reserved for future use SAMPLE PRELOAD 100 Captures I O ring contents Places the boundary scan regi...

Page 15: ... 5 P8 30 E10 55 B1 80 R2 6 R8 31 D10 56 A1 81 P3 7 R9 32 C11 57 C1 82 R3 8 P9 33 A11 58 D1 83 P2 9 P10 34 B11 59 E1 84 R4 10 R10 35 A10 60 F1 85 P4 11 R11 36 B10 61 G1 86 N5 12 H11 37 A9 62 D2 87 P6 13 N11 38 B9 63 E2 88 R6 14 M11 39 C10 64 F2 89 Internal 15 L11 40 A8 65 G2 16 K11 41 B8 66 H1 17 J11 42 A7 67 H3 18 M10 43 B7 68 J1 19 L10 44 B6 69 K1 20 K10 45 A6 70 L1 21 J10 46 B5 71 M1 22 H9 47 A5...

Page 16: ... U9 47 F10 82 B4 117 P1 13 P6 48 E10 83 C3 118 R2 14 W11 49 E11 84 B3 119 R1 15 W10 50 D11 85 A3 120 T2 16 V11 51 D10 86 A2 121 T1 17 V10 52 C11 87 A1 122 U2 18 U11 53 C10 88 B2 123 U1 19 U10 54 B11 89 B1 124 V2 20 T11 55 B10 90 C2 125 V1 21 T10 56 A11 91 C1 126 W2 22 R11 57 A10 92 D2 127 W1 23 R10 58 C9 93 D1 128 T6 24 P11 59 B9 94 E1 129 U3 25 P10 60 A9 95 E2 130 V3 26 N11 61 D8 96 F2 131 T4 27 ...

Page 17: ...V I O IOL 100 µA 0 2 V VIH Input HIGH Voltage 14 for 2 5V I O 1 7 VDD 0 3V V for 1 8V I O 1 26 VDD 0 3V V VIL Input LOW Voltage 14 for 2 5V I O 0 3 0 7 V for 1 8V I O 0 3 0 36 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 µA Input Current of MODE Input VSS 30 µA Input VDD 5 µA Input Current of ZZ Input VSS 5 µA Input VDD 30 µA IOZ Output Leakage Current GND VI VDDQ Output Disabled ...

Page 18: ...ance Junction to Ambient Test conditions follow standard test methods and procedures for measuring thermal impedance per EIA JESD51 25 21 20 8 25 31 C W ΘJC Thermal Resistance Junction to Case 2 58 3 2 4 48 C W AC Test Loads and Waveforms Note 16 Tested initially and after any design or process change that may affect these parameters OUTPUT R 317Ω R 351Ω 5 pF INCLUDING JIG AND SCOPE a b OUTPUT RL ...

Page 19: ... Chip Select Set up 1 2 1 4 1 5 ns Hold Times tAH Address Hold After CLK Rise 0 3 0 4 0 5 ns tDH Data Input Hold After CLK Rise 0 3 0 4 0 5 ns tCENH CEN Hold After CLK Rise 0 3 0 4 0 5 ns tWEH WE BWx Hold After CLK Rise 0 3 0 4 0 5 ns tALH ADV LD Hold after CLK Rise 0 3 0 4 0 5 ns tCEH Chip Select Hold After CLK Rise 0 3 0 4 0 5 ns Notes 17 This part has a voltage regulator internally tpower is th...

Page 20: ...ustrated CEN being used to create a pause A write is not performed during this cycle WRITE D A1 1 2 3 4 5 6 7 8 9 CLK t CYC tCL tCH 10 CE tCEH tCES WE CEN tCENH tCENS BWx ADV LD tAH tAS ADDRESS A1 A2 A3 A4 A5 A6 A7 tDH tDS Data In Out DQ tCLZ D A1 D A2 D A5 Q A4 Q A3 D A2 1 tDOH tCHZ tCO WRITE D A2 BURST WRITE D A2 1 READ Q A3 READ Q A4 BURST READ Q A4 1 WRITE D A5 READ Q A6 WRITE D A7 DESELECT OE...

Page 21: ...eselected when entering ZZ mode See cycle description table for all possible signal conditions to deselect the device 28 I Os are in High Z when exiting ZZ sleep mode Switching Waveforms continued t ZZ I SUPPLY CLK ZZ t ZZREC ALL INPUTS except ZZ DON T CARE I DDZZ t ZZI tRZZI Outputs Q High Z DESELECT or READ Only Feedback ...

Page 22: ...60AV25 167BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Lead Free CY7C1462AV25 167BZXI CY7C1464AV25 167BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm CY7C1464AV25 167BGXI 209 ball Fine Pitch Ball Grid Array 14 22 1 76 mm Lead Free 200 CY7C1460AV25 200AXC 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Commercial CY7C1462AV25 200AXC CY7C1460AV25 ...

Page 23: ...CY7C1460AV25 250AXI 51 85050 100 Pin Thin Quad Flat Pack 14 x 20 x 1 4 mm Lead Free Industrial CY7C1462AV25 250AXI CY7C1460AV25 250BZI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm CY7C1462AV25 250BZI CY7C1460AV25 250BZXI 51 85165 165 ball Fine Pitch Ball Grid Array 15 x 17 x 1 4 mm Lead Free CY7C1462AV25 250BZXI CY7C1464AV25 250BGI 51 85167 209 ball Fine Pitch Ball Grid Array 14 2...

Page 24: ...R SIDE 3 DIMENSIONS IN MILLIMETERS BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 0 30 0 08 0 65 20 00 0 10 22 00 0 20 1 40 0 05 12 1 1 60 MAX 0 05 MIN 0 60 0 15 0 MIN 0 25 0 7 8X STAND OFF R 0 08 MIN TYP 0 20 MAX 0 15 MAX 0 20 MAX R 0 08 MIN 0 20 MAX 14 00 0 10 16 00 0 20 0 10 SEE DETAIL A DETAIL A 1 100 30 31 50 51 80 81 GAUGE PLANE 1 00 REF 0 20 MIN SEATING PLANE 100 p...

Page 25: ...0 1 00 Ø0 45 0 05 165X Ø0 25 M C A B Ø0 05 M C B A 0 15 4X 0 35 1 40 MAX SEATING PLANE 0 53 0 05 0 25 C 0 15 C PIN 1 CORNER TOP VIEW BOTTOM VIEW 2 3 4 5 6 7 8 9 10 10 00 14 00 B C D E F G H J K L M N 11 11 10 9 8 6 7 5 4 3 2 1 P R P R K M N L J H G F E D C B A C 1 00 5 00 0 36 0 05 0 10 165 ball FBGA 15 x 17 x 1 4 mm 51 85165 51 85165 A Feedback ...

Page 26: ...ress written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifie...

Page 27: ...3 ns to 1 5 ns for 200 Mhz Speed Bin Added lead free information for 100 TQFP 165 FBGA and 209 FBGA packages B 331778 See ECN SYT Modified Address Expansion balls in the pinouts for 165 FBGA and 209 FBGA Package as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL VOH test conditions Changed CIN CCLK and CI O to 7 7and 6 pF from 5 5 and 7 pF for 165 FBGA Package Added In...

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