Cypress Semiconductor NoBL CY7C1460AV25, Manual

Page: 19 / 27

CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
Document #: 38-05354 Rev. *D Page 19 of 27
Switching Characteristics
Over the Operating Range
[21, 22]
Parameter Description
–250 –200 –167
Unit Min. Max. Min. Max. Min. Max.
t
Power
[17]
V
CC
(typical) to the first access read or write 1 1 1 ms
Clock
t
CYC
Clock Cycle Time 4.0 5.0 6.0 ns
F
MAX
Maximum Operating Frequency 250 200 167 MHz
t
CH
Clock HIGH 1.5 2.0 2.4 ns
t
CL
Clock LOW 1.5 2.0 2.4 ns
Output Times
t
CO
Data Output Valid After CLK Rise 2.6 3.2 3.4 ns
t
EOV
OE LOW to Output Valid 2.6 3.0 3.4 ns
t
DOH
Data Output Hold After CLK Rise 1.0 1.5 1.5 ns
t
CHZ
Clock to High-Z
[18, 19, 20]
2.6 3.0 3.4 ns
t
CLZ
Clock to Low-Z
[18, 19, 20]
1.0 1.3 1.5 ns
t
EOHZ
OE HIGH to Output High-Z
[18, 19, 20]
2.6 3.0 3.4 ns
t
EOLZ
OE LOW to Output Low-Z
[18, 19, 20]
0 0 0 ns
Set-up Times
t
AS
Address Set-up Before CLK Rise 1.2 1.4 1.5 ns
t
DS
Data Input Set-up Before CLK Rise 1.2 1.4 1.5 ns
t
CENS
CEN Set-up Before CLK Rise 1.2 1.4 1.5 ns
t
WES
WE, BW
x
Set-up Before CLK Rise
1.2 1.4 1.5 ns
t
ALS
ADV/LD Set-up Before CLK Rise 1.2 1.4 1.5 ns
t
CES
Chip Select Set-up 1.2 1.4 1.5 ns
Hold Times
t
AH
Address Hold After CLK Rise 0.3 0.4 0.5 ns
t
DH
Data Input Hold After CLK Rise 0.3 0.4 0.5 ns
t
CENH
CEN Hold After CLK Rise 0.3 0.4 0.5 ns
t
WEH
WE, BW
x
Hold After CLK Rise 0.3 0.4 0.5 ns
t
ALH
ADV/LD Hold after CLK Rise 0.3 0.4 0.5 ns
t
CEH
Chip Select Hold After CLK Rise 0.3 0.4 0.5 ns
Notes:
17. This part has a voltage regulator internally; t
power
is the time power needs to be supplied above V
DD
minimum initially, before a Read or Write operation can be
initiated.
18. t
CHZ
, t
CLZ
, t
EOLZ
, and t
EOHZ
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
19. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
20. This parameter is sampled and not 100% tested.
21. Timing reference is 1.25V when V
DDQ
= 2.5V and 0.9V when V
DDQ
= 1.8V.
22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
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