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CY7C1215H

Document #: 38-05666 Rev. *B

Page 7 of 15

Maximum Ratings

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Storage Temperature  ................................ –65

°

C to + 150

°

C

Ambient Temperature with
Power Applied............................................ –55

°

C to + 125

°

C

Supply Voltage on V

DD

 Relative to GND....... –0.5V to + 4.6V

Supply Voltage on V

DDQ

 Relative to GND ..... –0.5V to + V

DD

DC Voltage Applied to Outputs
in Tri-State........................................... –0.5V to V

DDQ

 + 0.5V

DC Input Voltage ................................... –0.5V to V

DD

 + 0.5V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage...........................................  >2001V
(per MIL-STD-883, Method 3015)

Latch-up Current.....................................................  >200 mA

Operating Range

Range

Ambient

Temperature

V

DD

V

DDQ

Commercial

0°C to +70°C 

3.3V

 

–5%/+10%

2.5V –5%

to

 

V

DD

Industrial

–40°C to +85°C 

Electrical Characteristics 

Over the Operating Range

[7, 8] 

Parameter

Description

Test Conditions

Min.

Max.

Unit

V

DD

Power Supply Voltage

3.135

3.6

V

V

DDQ

I/O Supply Voltage

for 3.3V I/O

3.135

V

DD

V

for 2.5V I/O

2.375

2.625

V

V

OH

Output HIGH Voltage

for 3.3V I/O, I

OH 

= –4.0 mA

2.4

V

for 2.5V I/O, I

OH 

= –1.0 mA

2.0

V

V

OL

Output LOW Voltage

for 3.3V I/O, I

OL 

= 8.0 mA

0.4

V

for 2.5V I/O, I

OL 

= 1.0 mA

0.4

V

V

IH

Input HIGH Voltage

[7]

for 3.3V I/O

2.0

V

DD 

+ 0.3V

V

for 2.5V I/O

1.7

V

DD 

+ 0.3V

V

V

IL

Input LOW Voltage

[7]

for 3.3V I/O

–0.3

0.8

V

for 2.5V I/O

–0.3

0.7

V

I

X

Input Leakage Current 
except ZZ and MODE

GND 

 V

I

 

 V

DDQ

–5

5

µ

A

Input Current of MODE

Input = V

SS

–30

µ

A

Input = V

DD

5

µ

A

Input Current of ZZ

Input = V

SS

–5

µ

A

Input = V

DD

30

µ

A

I

OZ

Output Leakage Current GND 

 V

I

 

 V

DDQ, 

Output Disabled

–5

5

µ

A

I

DD

V

DD

 Operating Supply 

Current

V

DD 

= Max., I

OUT 

= 0 mA,

f = f

MAX

 = 1/t

CYC

6-ns cycle,166 MHz

240

mA

7.5-ns cycle, 133 MHz

225

mA

I

SB1

Automatic CS 
Power-down 
Current—TTL Inputs

V

DD 

= Max, Device Deselected, 

V

IN

 

 V

IH

 or V

IN

 

 V

IL

f = f

MAX

 = 1/t

CYC

6-ns cycle,166 MHz

100

mA

7.5-ns cycle, 133 MHz

90

mA

I

SB2

Automatic CS
Power-down 
Current—CMOS Inputs

V

DD 

= Max, Device Deselected, 

V

IN

 0.3V or V

IN

 > V

DDQ

 – 0.3V, 

f = 0

All speeds

40

mA

I

SB3

Automatic CS 
Power-down 
Current—CMOS Inputs

V

DD 

= Max, Device Deselected, or 

V

IN

 

 0.3V or V

IN

 > V

DDQ

 – 0.3V

f = f

MAX

 = 1/t

CYC

6-ns cycle,166 MHz

85

mA

7.5-ns cycle, 133 MHz

75

mA

I

SB4

Automatic CS
Power-down 
Current—TTL Inputs

V

DD 

= Max, Device Deselected, 

V

IN

 

 V

IH

 or V

IN

 

 V

IL

, f = 0

All speeds

45

mA

Notes: 

7. Overshoot: V

IH

(AC) < V

DD

 +1.5V (Pulse width less than t

CYC

/2), undershoot: V

IL

(AC) > –2V (Pulse width less than t

CYC

/2).

8. T

Power-up

: Assumes a linear ramp from 0V to V

DD

(min.) within 200 ms. During this time V

IH

 < V

DD

 and V

DDQ 

< V

DD

.

[+] Feedback 

Summary of Contents for CY7C1215H

Page 1: ...nous inputs include the Output Enable OE and the ZZ pin Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor ADSP or Address Strobe Controller ADSC ar...

Page 2: ...Q VDDQ DQA DQA NC NC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC A A CE 1 CE 2 BW D BW C BW B BW A CE 3 V DD V SS CLK GW BW...

Page 3: ...as input data pins OE is masked during the first clock of a Read cycle when emerging from a deselected state ADV Input Synchronous Advance Input signal sampled on the rising edge of CLK active LOW Wh...

Page 4: ...esented to the DQ inputs is written into the corre sponding address location in the memory array If GW is HIGH then the Write operation is controlled by BWE and BW A D signals The CY7C1215H provides B...

Page 5: ...ad Continue Read Next L H X X X H L H Tri State Read Continue Read Next L H X X X H L L DQ Read Suspend Read Current L X X X H H H H Tri State Read Suspend Read Current L X X X H H H L DQ Read Suspend...

Page 6: ...te Byte A DQA H L H H H L Write Byte B DQB H L H H L H Write Bytes B A H L H H L L Write Byte C DQC H L H L H H Write Bytes C A H L H L H L Write Bytes C B H L H L L H Write Bytes C B A H L H L L L Wr...

Page 7: ...ge 7 for 3 3V I O 2 0 VDD 0 3V V for 2 5V I O 1 7 VDD 0 3V V VIL Input LOW Voltage 7 for 3 3V I O 0 3 0 8 V for 2 5V I O 0 3 0 7 V IX Input Leakage Current except ZZ and MODE GND VI VDDQ 5 5 A Input C...

Page 8: ...llow standard test methods and procedures for measuring thermal impedance per EIA JESD51 30 32 C W JC Thermal Resistance Junction to Case 6 85 C W AC Test Loads and Waveforms Note 9 Tested initially a...

Page 9: ...se 0 5 0 5 ns tADH ADSP ADSC Hold after CLK Rise 0 5 0 5 ns tADVH ADV Hold after CLK Rise 0 5 0 5 ns tWEH GW BWE BW A D Hold after CLK Rise 0 5 0 5 ns tDH Data Input Hold after CLK Rise 0 5 0 5 ns tCE...

Page 10: ...CE3 is HIGH tCYC t CL CLK ADSP t ADH t ADS ADDRESS t CH OE ADSC CE tAH tAS A1 tCEH tCES GW BWE BW A D Data Out Q High Z tCLZ tDOH tCO ADV tOEHZ tCO Single READ BURST READ tOEV tOELZ tCHZ ADV suspends...

Page 11: ...ADS ADDRESS tCH OE ADSC CE tAH tAS A1 tCEH tCES BWE BW A D Data Out Q High Z ADV BURST READ BURST WRITE D A2 D A2 1 D A2 1 D A1 D A3 D A3 1 D A3 2 D A2 3 A2 A3 Data In D Extended BURST WRITE D A2 2 Si...

Page 12: ...e is performed 19 GW is HIGH Switching Waveforms continued tCYC tCL CLK ADSP tADH tADS ADDRESS tCH OE ADSC CE tAH tAS A2 tCEH tCES BWE BW A D Data Out Q High Z ADV Single WRITE D A3 A4 A5 A6 D A5 D A6...

Page 13: ...entering ZZ mode See Cycle Descriptions table for all possible signal conditions to deselect the device 21 DQs are in High Z when exiting ZZ sleep mode Switching Waveforms continued t ZZ I SUPPLY CLK...

Page 14: ...ed trademark of IBM Corporation All product and company names mentioned in this document may be trademarks of their respective holders Ordering Information Not all of the speed package and temperature...

Page 15: ...poration on Page 1 from 3901 North First Street to 198 Champion Court Added 2 5VI O option Changed Three State to Tri State Included Maximum Ratings for VDDQ relative to GND Modified Input Load to Inp...

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