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CY25822-2

Document #: 38-07531  Rev. **

Page 7 of 9 

t

FALLL1

Falling Edge Rate

Measured from 2.4V to 0.4V
REFOUT and CLOCKOUT

1.33

4.0

V/ns

Low Buffer Strength
Refer to I

2

C Control

t

RISEH2

Rise Time

Measured from 0.4V to 2.4V
REFOUT and CLOCKOUT

0.4

1.0

ns

High Buffer Strength
Refer to I

2

C Control

t

FALLH2

Fall Time

Measured from 2.4V to 0.4V
REFOUT and CLOCKOUT

0.4

1.0

ns

High Buffer Strength
Refer to I

2

C Control

t

RISEL2

Rise Time

Measured from 0.4V to 2.4V
REFOUT and CLOCKOUT

0.5

1.5

ns

Low Buffer Strength
Refer to I

2

C Control

t

FALLL2

Fall Time

Measured from 2.4V to 0.4V
REFOUT and CLOCKOUT

0.5

1.5

ns

Low Buffer Strength
Refer to I

2

C Control

T

CYC1

Cycle to Cycle Jitter

REFOUT

500

ps

SSCG is ON 

T

CYC2

Cycle to Cycle Jitter

CLOCKOUT

250

ps

SSCG is ON

LTJ

10

µ

S Period Jitter 

(100KHz, Frequency Mod-
ulation Amplitude)

Applies to REFOUT at all 
times and CLOCKOUT when 
SSCG is Off

2.0

ns

t

START

Start up time

From VDD = 2.0 V

3.0

ms

All outputs disabled

Table 7. AC Parameters (T

A

 = 0°C to +70°C, V

DD

 = 3.3V ± 5%)  (continued)

Parameter

Description

Conditions

Min.

Max.

Unit

Notes

Table 8. Signal Loading Table

Clock Name

Max Load (pF)

CLKOUT, REFOUT

15

Ordering Information

Part Number

Package Type

Product Flow

CY25822SC–2

8-pin SOIC

Commercial, 0°C to 70°C

CY25822SC–2T

8-pin SOIC – Tape and Reel

Commercial, 0°C to 70°C

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Summary of Contents for CY25822-2

Page 1: ...ter I2 C programmability 500 A power down current SpreadSpectrumforbest electromagnetic interference EMI reduction 8 pin SOIC package Block Diagram Pin Configuration 1 2 3 4 8 7 6 5 C LK IN V D D G N...

Page 2: ...is 11010100 D4h Pin Description Pin No Pin Name Pin Type Pin Description 1 CLKIN Input 48 MHz or 66 MHz Clock Input 2 VDD Power Power Supply for PLL and Outputs 3 GND Ground Ground for Outputs 4 CLKO...

Page 3: ...yte operation bits 6 0 of the command code represents the offset of the byte to be accessed 19 Acknowledge from slave 19 Acknowledge from slave 20 27 Data byte from master 8 bits 20 Repeat start 28 Ac...

Page 4: ...topped in the driven state are driven low The CLKIN input must be on and within specified operating parameters before PWRDWN is asserted and it must remain in this state while PWRDWN is asserted 0 1 0...

Page 5: ...shutdown clock is driven low ALL clocks need to be stopped in a predictable manner All clocks need to be shutdown without any glitches or other abnormal behavior while transitioning to a stopped stat...

Page 6: ...Single edge is required to be monotonic when transi tioning through this region CIN Input Pin Capacitance 5 pF COUT Output Pin Capacitance 6 pF LIN Pin Inductance 7 nH TA Ambient Temperature 0 70 C N...

Page 7: ...sured from 2 4V to 0 4V REFOUT and CLOCKOUT 0 5 1 5 ns Low Buffer Strength Refer to I2 C Control TCYC1 Cycle to Cycle Jitter REFOUT 500 ps SSCG is ON TCYC2 Cycle to Cycle Jitter CLOCKOUT 250 ps SSCG i...

Page 8: ...ay reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor products in life support systems application implies that the manufacturer assumes all risk...

Page 9: ...ev Page 9 of 9 Document History Page Document Title CY25822 2 CK SSC Spread Spectrum Clock Generator Document Number 38 07531 REV ECN NO Issue Date Orig of Change Description of Change 124462 03 19 03...

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