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CY25822-2

Document #: 38-07531  Rev. **

Page 3 of 9 

   

....

Data Byte N –8 bits

56

Acknowledge

....

Acknowledge from slave

....

Data bytes from slave/Acknowledge

....

Stop

....

Data byte N from slave – 8 bits

....

Not Acknowledge

....

Stop

Table 2. Block Read and Block Write Protocol  (continued)

Table 3. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Bit

Description

Bit

Description 

1

Start

1

Start

2:8

Slave address – 7 bits

2:8

Slave address – 7 bits

9

Write = 0

9

Write = 0

10

Acknowledge from slave

10

Acknowledge from slave

11:18

Command Code – 8 bits 
'1xxxxxxx' stands for byte operation, bits[6:0] of 
the command code represents the offset of the 
byte to be accessed

11:18

Command Code – 8 bits
'1xxxxxxx' stands for byte operation, bits[6:0] 
of the command code represents the offset of 
the byte to be accessed

19

Acknowledge from slave

19

Acknowledge from slave

20:27

Data byte from master – 8 bits

20

Repeat start

28

Acknowledge from slave

21:27

Slave address – 7 bits

29

Stop

28

Read = 1

29

Acknowledge from slave

30:37

Data byte from slave – 8 bits

38

Not Acknowledge

39

Stop

Byte 0: Control Register

Bit

@Pup

Pin#

Name

Pin Description

7

1

4

SS0

6

0

4

SS1

5

0

4

SS2

4

0

4

SS3

3

1

Not Applicable

Reserved, must be written as 1

2

1

4,  5

CLKOUT, 
REFOUT

Power-down three-state enable
0 = three-state outputs, 1 = drive outputs low
(Applies only in Power Down State)

1

1

4

CLKOUT

Spread Spectrum enable
0 = spread off, 1 = spread on

0

0

Not Applicable 

No Pins

Table 4. Spread Spectrum Select 

SS3

SS2

SS1

SS0

Spread Mode

Spread Amount%

0

0

0

0

Down

0.8

0

0

0

1

Down

1.0

0

0

1

0

Down

1.25

0

0

1

1

Down

1.5

0

1

0

0

Down

1.75

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Summary of Contents for CY25822-2

Page 1: ...ter I2 C programmability 500 A power down current SpreadSpectrumforbest electromagnetic interference EMI reduction 8 pin SOIC package Block Diagram Pin Configuration 1 2 3 4 8 7 6 5 C LK IN V D D G N...

Page 2: ...is 11010100 D4h Pin Description Pin No Pin Name Pin Type Pin Description 1 CLKIN Input 48 MHz or 66 MHz Clock Input 2 VDD Power Power Supply for PLL and Outputs 3 GND Ground Ground for Outputs 4 CLKO...

Page 3: ...yte operation bits 6 0 of the command code represents the offset of the byte to be accessed 19 Acknowledge from slave 19 Acknowledge from slave 20 27 Data byte from master 8 bits 20 Repeat start 28 Ac...

Page 4: ...topped in the driven state are driven low The CLKIN input must be on and within specified operating parameters before PWRDWN is asserted and it must remain in this state while PWRDWN is asserted 0 1 0...

Page 5: ...shutdown clock is driven low ALL clocks need to be stopped in a predictable manner All clocks need to be shutdown without any glitches or other abnormal behavior while transitioning to a stopped stat...

Page 6: ...Single edge is required to be monotonic when transi tioning through this region CIN Input Pin Capacitance 5 pF COUT Output Pin Capacitance 6 pF LIN Pin Inductance 7 nH TA Ambient Temperature 0 70 C N...

Page 7: ...sured from 2 4V to 0 4V REFOUT and CLOCKOUT 0 5 1 5 ns Low Buffer Strength Refer to I2 C Control TCYC1 Cycle to Cycle Jitter REFOUT 500 ps SSCG is ON TCYC2 Cycle to Cycle Jitter CLOCKOUT 250 ps SSCG i...

Page 8: ...ay reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor products in life support systems application implies that the manufacturer assumes all risk...

Page 9: ...ev Page 9 of 9 Document History Page Document Title CY25822 2 CK SSC Spread Spectrum Clock Generator Document Number 38 07531 REV ECN NO Issue Date Orig of Change Description of Change 124462 03 19 03...

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