CyberResearch STH 15B Series, User Manual

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User Manual version 4.11
STH 15B Series
9-110
A
PPENDIX
A: Programming the Watchdog Timer
The STH 15B features a watchdog timer that can generate
a system reset if the CPU processing comes to a halt. This
feature ensures the system dependability during unattended
operation.
The following is the Watchdog Timer instruction:
IOW 444(Hex),Timer(Hex) ---------
Enable/Setting/refresh Watchdog Timer
Timer: 64 levels setting (1 ~ 64 seconds, tol-20%)
IOR 441(Hex) --------------------------
Disable Watchdog Timer
If you want to use the watchdog timer, you must write a
program which writes I/O port address 444(Hex) at timer
setting intervals. The first time your program writes the port,
it sets and enables the watchdog timer. Program must write
the port at time intervals. Otherwise the watchdog timer will
activate and reset the CPU. When you want to disable the
watchdog timer, your program should read I/O port
441(Hex).
If CPU processing come to a standstill because of a software
bug or EMI, program’s signals to I/O port address 444(Hex)
to the timer will be interrupted. The watchdog timer will
automatically reset the CPU, and data processing will
continue normally.