I.L.
29-8858
9.0 R EFERENCES
9.1 Digitrip RMS Trip Assemblies
I . L. 29-885
I . L. 29-886
I . L. 29-888
Instructions for Digitrip RMS 51 0 Trip Unit
I nstructions for Digitrip RMS 61 0 Trip Unit
Instructions for Digitrip RMS 81 0 Trip Unit
9.2 Type OS Low-Voltage AC Power Circuit Breakers
I. B . 33-790-1
I nstructions for Low-Voltage Power Circuit
Breakers Types DS and DSL
I. B. 33-790- 1
AD 32-870
SC-561 9-93
SC-5620-93
SC-5621 -93
508B508
Supplement B to Digitrip RMS Trip Units
Typical Time-Current Characteristic Curves
for Types DS and DSL Circuit Breakers
I nstantaneous (I)
Long Delay and Short Delay (LS)
Ground (G)
Connection Diagram for Type DS Circuit
Breakers
9.3 Type SPB Systems Pow-R Breakers
I . L. 29-801
I nstruction for the Systems Pow-R Breaker
and Drawout Mechanism
I.L. 29-849
Supplementary I nstructions for the Sys
tems Pow-R Breaker used with the Digitrip
RMS Trip Units
AD 29-863
Typical Time-Current Characteristic Curves
for Type SPB Systems Pow-R Breaker
SC-5623-93
Instantaneous (I)
SC-5624-93
Long Delay and Short Delay (LS)
SC-5625-93
G round (G)
I.S. 1 5545
SPB Master Connection Diagram
9.4 Series
c®
R-Frame Molded Case Circuit Breakers
29C1 06
29C1 07
29C7 1 3
A D 29- 1 67 R
SC-5626-93
SC-5627-93
SC-5628-93
Effective May 1 997
Frame Book
Frame Instruction Leaflet
Supplementary Instructions for Series
c®
R-Frame used with the Digitrip RMS Trip
Units
Typical Time-Current Characteristic Curves
for R-Frame Circuit Breakers
I nstantaneous (I)
Long Delay and Short Delay (LS)
Ground (G)
Page 1 5
I . L. 29C7 1 4
Master Connection Diagram for Series
c®
R-Frame Circuit Breaker
APPENDIX A ZONE INTERLOCKING
Assume
a ground fault of 2000 Amperes occurs and
refer to Fig A.1 .
CASE 1 : There is no Zone Selective Interlocking.
(standard time delay coordination is used)
Fault 3
The branch breaker will trip clearing the fault i n
0 . 1 s.
Fau lt 2
The feeder breaker will trip clearing the fault in
0.3 s.
Fault 1
The breaker will trip clearing the fault in 0.5 s.
CASE 2: There is Zone Selective Interlocking
Fault 3
The branch breaker trip u nit will initiate the trip i n
0.03 s to clear the fault and Z 3 will send a n inter
locking signal to the Z2 trip unit; and Z2 will send
an interlocking signal to Z1 .
Z1 and Z2 trip units will begin to time out, and in
the event that the branch breaker Z3 would not
clear the fault, the feeder breaker Z2 will clear the
fault in 0.3 s (as above). Similarly, in the event that
the feeder breaker Z2 would not clear the fault, the
main breaker Z1 wil l clear the fault in 0.5 s (as
above).
Fault 2
The feeder breaker trip u nit will initiate the trip i n
0.03 s to clear the fault; and Z2 will send a n inter
locking signal to the
Z1 trip u nit. Z1 trip u nit will
begin to time out, and in the event that the feeder
breaker Z2 would not clear the fault, the main
breaker Z1 will clear the fau lt in 0.5 s (as above).
Fault 1
There are no interlocking signals. The main
breaker trip u nit will initiate the trip in 0.03 s.
Figure A.2 presents a Zone Selective I nterlocking con
nection d iagram tor a system with two main breakers
from incoming sources and a bus tie breaker. Note the
blocking diode D1 is needed so that the feeder breakers
can send interlocking signals to both the main and tie
breakers, without having the tie breaker send itself an
interlocking signal.
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