Contec SLC-8550-LVA, User Manual

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8. BIOS Setup
54 SLC-8550-LVA
Description Choice
CAS Latency Time
When synchronous DRAM is installed, the
number of clock cycles of CAS latency depends
on the DRAM timing. Do not reset this field
from the default value specified by the system
designer.
You can select CAS latency time in HCLK of
2/2 or 3/3. The system board designer should set
the values in this field, depends on the DRAM
installed specifications of the installed DRAM
or the installed CPU.
Active to Precharge delay
Select the precharge delay timer.
DRAM RAS# to CAS# delay
This field lets you insert a timing delay between
the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed.
Fast gives faster performance; and Slow gives
more stable performance. This field applies only
when synchronous DRAM is installed in the
system.
DRAM RAS# Precharge
The precharge time is the number of cycles it
takes for the RAS to accumulate its charge
before DRAM refresh. If insufficient time is
allowed, refresh may be incomplete and the
DRAM may fail to retain data.